Remediation method for unsuccessfully formed interconnected through holes on wafer
A technology for interconnecting through-holes and wafers, which is applied in the fields of electrical components, semiconductor/solid-state device manufacturing, circuits, etc. It can solve problems such as increased production costs, scrapped wafers, and patterns that do not meet the requirements, so as to ensure quality and ensure good products rate and the effect of avoiding economic loss
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[0026] In order to make the purpose and features of the present invention more obvious and understandable, the present invention will be further described by giving preferred embodiments and in conjunction with the accompanying drawings.
[0027] See figure 2 , which is a flow chart of a remedy method for failure to form interconnect vias on a wafer provided by an embodiment of the present invention. Please refer to Figure 3A to Figure 3E , wherein the wafer includes: a substrate 100 , and a dielectric layer 200 formed with a through hole 300 on the substrate 100 .
[0028] In this embodiment, the dielectric layer 200 used to form the via hole is a silicon oxide layer with a thickness greater than For example In the via hole etching process, due to various reasons, the via hole etching fails, and the pattern deformation of the formed via hole does not meet the requirements of the device. If the depth of the via hole 310 and the dielectric layer of the corresponding part...
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