Semiconductor memory device

Abstract

The invention provides a semiconductor memory device. With respect to memory that applies bit line step-down technology, an IO block (2) is provided with: a first transistor (TR1) that controls the potential of a first bit line (BL / NBL) provided for a memory cell line; and a first logic gate (LG1) that controls the first transistor (TR1). The drain or the source of the first transistor (TR1) and the input of the first logic gate (LG1) are connected, the gate of the first transistor (TR1) and the output of the first logic gate (LG1) are connected, and the first transistor (TR1) is pulse-driven. In addition, a data readout circuit (11) is provided only on one of the bit lines (BL).

Description

technical field [0001] The present invention relates to a semiconductor memory device, in particular to a technology for controlling the potential of a bit line of a memory circuit. Background technique [0002] Conventionally, in order to improve the SNM (Static Noise Margin) of the memory cell of the SRAM (Static Random Access Memory), there is known a method in which an N-channel MOS (NMOS) transistor connected to a bit line is pulse-driven to lower the voltage of the bit line. technology. Among them, as a data reading method, a sense amplifier that detects a slight potential difference between a pair of bit lines is used (see Non-Patent Document 1). [0003] On the other hand, there is also known a technique for controlling the potential level of a signal line by using a decoding circuit unit for driving a word line of a semiconductor memory device (see Patent Document 1). [0004] Patent Document 1: Japanese Patent Laid-Open No. 2007-164922 [0005] Non-Patent Docume...

AI Technical Summary

Problems solved by technology

However, when the power supply voltage is Vdd and the threshold voltage of the NMOS transistor is Vtn, a long precharge time is required to raise the potential of the signal line to Vdd-Vtn through the NMOS transistor.

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