Semiconductor memory

Abstract

A semiconductor memory device has a memory cell array (1) including memory cells (MC); a reference current generating circuit (DMC) which generates a reference current (Iref); a reference voltage generating circuit (6) which generates a reference voltage in a reference node (RSN) on the basis of the reference current (Iref) generated by the reference current generating circuit; a first sense circuit (4a) which generates an output current (2Icell) on the basis of a cell current (Icell) of the selected memory cell and which generates a data potential in a sense node (SN) on the basis of the output current and the reference current; and a second sense circuit (4b) which detects the data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.

Description

(1) Technical field [0001] The present invention relates to a semiconductor memory having a current sense type memory cell in which data is judged based on the presence or absence or magnitude of a cell current, and more particularly to a data readout circuit. (2) Background technology [0002] In conventional DRAMs, memory cells are formed using MISFETs and capacitors. With the adoption of the trench capacitor structure or stacked capacitor structure, the miniaturization of DRAM has made great progress, and the current unit cell size has been reduced to 8F with the minimum processing size as F. 2 area. However, it is becoming more and more difficult to ensure the same trend of cell size reduction as in the past. Here, there are technical difficulties in that the transistor must be made into a vertical transistor, the problem of increased interference between adjacent cells, and manufacturing technical difficulties such as processing and film formation. [0003] On the ot...

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Problems solved by technology

[0012] However, the structure of (1) is complicated, and it is difficult to control the characteristics because of the use of parasitic transistors.

Although the structure of (2) is simple, the drain and source of the transistor must be connected to the signal line for potential control

In addition, due to the well isolation, the cell size is large, and each bit cannot be rewritten individually

In (3), it is necessary to control the potential from the side of the SOI substrate, therefore, it is impossible to rewrite each bit individually, and there is a difficulty in controllability

(4) It must be made into a special transistor structure. In addition, in the memory cell, since there must be word lines, write bit lines, read bit lines, and clear lines, the number of signal lines is large

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