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Film magnetic storage device with data write-in by applying magnetic field

A storage device and data writing technology, applied in the direction of digital memory information, magnetic field controlled resistors, information storage, etc., can solve problems such as wrong data writing, achieve the effect of preventing data wrong writing and improving operation reliability

Inactive Publication Date: 2006-07-05
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0028] However, in excess of the switching field H SW In the non-selected memory cells to which only these unidirectional data writing magnetic fields are applied, data writing may be erroneously performed when magnetic noise along one direction is further applied.

Method used

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  • Film magnetic storage device with data write-in by applying magnetic field
  • Film magnetic storage device with data write-in by applying magnetic field
  • Film magnetic storage device with data write-in by applying magnetic field

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0098] refer to figure 1 The MRAM device 1 of the embodiment of the present invention performs random access in response to an external control signal CMD and a signal line ADD, and performs input of read data DIN and output of read data DOUT.

[0099] The MRAM device 1 has a memory array 2 in which a plurality of MTJ memory cells are arranged in rows and columns, and peripheral circuits 5a, 5b, and 5c are arranged in the peripheral region of the memory array 2 in order to read and write data to the memory array 2. . In addition, hereinafter, the peripheral circuits 5a, 5b, and 5c are collectively referred to as the peripheral circuit 5 or the peripheral circuit 5#.

[0100] The structure of memory array 2 will be described in detail later, but a plurality of write word lines WWL and read word lines RWL are arranged corresponding to rows of MTJ memory cells (hereinafter also simply referred to as “memory cell rows”). In addition, bit lines BL are arranged corresponding to c...

Embodiment 2

[0186] As explained in the item of the prior art, in the MRAM device, when data is written to the selected memory cell, for the non-selected memory cell belonging to the same memory cell row as the selected memory cell, only in the hard-to-magnetize axis In the (HA) direction, a predetermined data writing magnetic field is applied. Similarly, a predetermined data writing magnetic field is applied only to one side of the easy magnetization axis (EA) to an unselected memory cell belonging to the same memory cell column as the selected memory cell.

[0187] In each tunnel magnetoresistive element TMR, the free magnetization layer VL is magnetized in the direction corresponding to the level ("1" or "0") of the stored data along the easy axis (EA) direction, so it is most prone to error The non-selected memory cells in which the magnetization direction of the free magnetization layer VL is rewritten, that is, data is erroneously written, are memory cell groups associated with the s...

Embodiment 3

[0215] As described in the second embodiment, the magnetic noise from the power supply wiring becomes maximum when a peak current flows. Generally, for power supply wiring, decoupling capacitors are placed to suppress power supply fluctuations. A high-frequency current such as a peak current flowing through the power supply wiring passes through this decoupling capacitor. The decoupling capacitor occupies a relatively large area because it needs to have a certain amount of capacitor. Therefore, from the viewpoint of miniaturization and high integration of MRAM devices, it is important to efficiently arrange decoupling capacitors.

[0216] Figure 19 as well as Figure 20 It is a block diagram illustrating the first and second arrangement examples of decoupling capacitors in Embodiment 3, respectively.

[0217] refer to Figure 19 The power supply voltage lines PL are arranged, for example, along the column direction, and transmit the power supply voltage Vcc input to the ...

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Abstract

A peripheral circuitry is provided adjacent to a memory array and conducts read and write operations from and to the memory array. A power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry supply a power supply voltage and a ground voltage, respectively. The power supply voltage line and the ground line are arranged so that a magnetic field generated by a current flowing through the power supply voltage line and a magnetic field generated by a current flowing through the ground line cancel each other in the memory array.

Description

technical field [0001] The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including a memory cell including a magnetic tunnel junction (MTJ: Magnetic Tunnel Junction). Background technique [0002] An MRAM (Magnetic Random Access Memory) device is attracting attention as a memory device capable of nonvolatile data storage with low power consumption. The MRAM device is a storage device that performs nonvolatile data access using a plurality of thin-film magnetic bodies formed on a semiconductor integrated circuit, and performs random access for each of the thin-film magnetic bodies. [0003] In particular, in recent years, the performance of MRAM devices has been rapidly improved by using thin-film magnetic materials utilizing magnetic tunnel junctions as memory cells. MRAM device with memory cells including magnetic tunnel junctions, disclosed in "A 10ns Read and Write Non-Volatile MemoryArray Using a Magneti...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/15G11C11/14G11C11/16H01L21/8246H01L27/10H01L27/105H01L43/08
CPCG11C11/15G11C11/16G11C5/063G11C11/1697
Inventor 日高秀人
Owner RENESAS ELECTRONICS CORP
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