Method for establishing space correlation model of technical error in integrated circuit chip

Abstract

The invention belongs to the field of integrated circuits, relating to a method for establishing a space correlation model of technical errors in an integrated circuit chip. The method comprises the following steps of: extracting an unknown parameter of a space correlation function by utilizing the maximum likelihood estimation of a multi-test chip, and establishing the space correlation model of the errors in the chip; and multiplying a likelihood function of all test chips to obtain a joint likelihood function, solving through maximizing the joint likelihood function to obtain the space correlation function which is determined by a parameter value and can be directly used for circuit analysis design of the technical errors. The influence of pure random part of the error in the chip and the measurement error can be processed in the extraction process of the space correlation function, and the precision of an extracted result is remarkably improved. Determinant logarithms of symmetrical positive definite matrixes in the joint likelihood function are calculated by utilizing an LU (Logic Unit), and the problem of unstable number value occurring in direct calculation is solved.

Description

technical field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a method for establishing a spatial correlation model of process deviation in an integrated circuit chip. Background technique

[0002] With the rapid development of integrated circuit manufacturing technology, the feature size of integrated circuit chips is continuously reduced. Today, the characteristic size of integrated circuit MOS tubes has reached the nanometer level, and the semiconductor manufacturing industry has entered the era of nanotechnology. Under the complex nano-manufacturing process, the geometric and electrical parameter characteristic values ​​of integrated circuit devices and interconnection lines (such as the effective channel length of MOS transistors, interconnection line width and height, threshold voltage, etc.) Simple, definite design nominal values, but some form of probability density distribution around the nominal values. This proces...

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