ESD protection device in CMOS integrated circuit

Abstract

The invention discloses an electronic static discharge (ESD) protection device in a complementary metal oxide semiconductor (CMOS) integrated circuit, belongs to the field of analog circuits, and relates to an ESD protection system in the CMOS integrated circuit. The invention aims to provide the novel ESD protection system in the CMOS integrated circuit. A grid is grounded through a resistor Rg so that a grid coupling negative-channel metal oxide semiconductor (GCNMOS) is shut down when a complementary metal oxide semiconductor integrated circuit (CMOSIC) works, and the other negative-channel metal oxide semiconductor (NMOS) is connected as a capacitive Cc to reinforce the capacitive coupling effect; and when a positive ESD voltage occurs on an input PAD, a part of positive voltage is coupled to the grid of the GCNMOS through the Cd and the Cc, the grid voltage is discharged to the ground through the Rg, the size of the Rg affects the holding time of the grid voltage, and the GCNMOS is uniformly conducted so as to promote the ESD protection capability.

Description

Technical field: [0001] The invention belongs to the field of analog circuits, and relates to an ESD protection system in a CMOS integrated circuit. Background technique: [0002] Static electricity is ubiquitous in the process of chip manufacturing, packaging, testing and use. The accumulated static charge is released in nanoseconds to microseconds with a current of several amperes or tens of amperes. The instantaneous power is as high as hundreds of kilowatts, and the discharge energy It can reach millijoules, and the destruction intensity of the chip is extremely high. Therefore, the design of the electrostatic protection module in chip design is directly related to the functional stability of the chip, which is extremely important. With the development of the process, the feature size of the device is gradually reduced, and the gate oxide is also proportionally reduced. The dielectric strength of silicon dioxide is approximately 8×106V / cm, so the breakdown voltage of a...

AI Technical Summary

Problems solved by technology

The dielectric strength of silicon dioxide is approximately 8×106V / cm, so the breakdown voltage of a gate oxide with a thickness of 10nm is about 8V. Although the breakdown voltage is more than double the power supply voltage of 3.3V, various Static electricity caused by various factors generally has a peak voltage far exceeding 8V; The resistance is reduced, and the ESD protection ability is greatly weakened

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