Manufacturing process of whole gold-plated panel

A technology of manufacturing process and gold-plated area, which is applied in the field of manufacturing process of full-plate gold-plated plate, and can solve problems such as gold-plated penetration, poor quality of gold-plated, and collapse of gold-plated area

Inactive Publication Date: 2011-04-20
SHENNAN CIRCUITS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The main technical problem to be solved by the present invention is to provide a manufacturing process for a full-plate gold-plated plate, whic

Method used

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  • Manufacturing process of whole gold-plated panel
  • Manufacturing process of whole gold-plated panel
  • Manufacturing process of whole gold-plated panel

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[0032] In order to describe in detail the technical content, structural features, achieved objectives and effects of the present invention, the following is a detailed description in conjunction with the embodiments and accompanying drawings.

[0033] See Figure 1 ~ Figure 7 , The manufacturing process of the full-board gold-plated plate of the present invention includes the following steps:

[0034] a. Make all on-board graphics with gold-plated area 10 and non-gold-plated area 11 on the circuit board at one time;

[0035] b. A metal conductive layer with a thickness of 0.3um~0.8um is deposited on the whole board circuit board with all the patterns in the board; at this time, the gold-plated area becomes the metal conductive layer 13 covered with the metal conductive layer, The non-gold-plated area 11 becomes a metal conductive layer 12 covered with a metal conductive layer;

[0036] c. Paste a protective dry film on the non-gold-plated area coated with the metal conductive layer t...

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Abstract

The invention discloses a manufacturing process of a whole gold-plated panel, comprising the following steps: a. all in-panel graphs with gold-plated regions and non gold-plated regions are manufactured on a circuit board by one time; b. a metal conducting layer with the thickness of 0.3-0.8mu m is coated on the circuit board of the whole panel with manufactured in-panel graphs in a settling way; c. a protective dry film is adhered on the non gold-plated region coated with a metal conducting layer to protect the non gold-plated region, and the gold-plated region coated with a metal conducting layer is exposed; d. the coated metal conducting layer is utilized for electric conduction, and gold plating is carried out on the gold-plated region of the circuit board; e. the protective dry film on the non gold-plated region, which is flushed and soaked by 3-5 percent NaOH for 2-5 minutes, is removed; and f. a sodium peroxydisulfate solution is used for removing the metal conducting layer on the non gold-plated region through microetching. The process in the invention overcomes the disadvantages of gold plating diffusion coating, under etching, poor gold plating quality, collapsed gold plating regions and process limitations in the prior art.

Description

technical field [0001] The invention relates to a manufacturing process of a full-plate gold-plated plate. Background technique [0002] The existing full-board gold-plated board manufacturing process adopts the gold-plated process before graphics, and its technological process is as follows: blanking-inner layer processing-lamination-drilling-copper sinking-electroplating-outer layer graphics (use a large copper surface as a gold-plated wire , develop the gold-plated area for gold-plating)-full-board gold-plating-external alkali etching (remove all protective films, etch non-gold-plated areas)-external inspection-solder mask-character-surface coating-shape-electrical test-inspection- Package. [0003] However, the pre-patterning process has the following drawbacks: [0004] a. It is easy to be gold-plated, permeated, and etched clean: use a large copper surface as a gold-plated wire, and use a dry film to cover the non-gold-plated area. Because there are certain problems ...

Claims

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Application Information

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IPC IPC(8): H05K3/18H05K3/24
Inventor 刘宝林王成勇武凤伍罗斌崔荣
Owner SHENNAN CIRCUITS
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