[0068] The present invention will be described in detail below with reference to the drawings, in which preferred embodiments of the present invention are shown. The present invention can, but be embodied in different ways, but should not be limited to the embodiments described herein. For example, the description here refers more to N-channel trench MOSFETs, but it is obvious that other devices are also possible.
[0069] Reference image 3 As shown in a preferred embodiment of the present invention, the N-type epitaxial layer 202 is formed on the N+ substrate 200, and a drain metal 290 is deposited on the lower surface of the N+ substrate 200. In the N-type epitaxial layer 202, there are a plurality of first trench gates 210 located in the active area, at least one wider second trench gate 212 for gate connection, and at least three second trench gates located in the terminal area. Three trench gate 211. The inner surfaces of the first trench gate 210, the second trench gate 212, and the third trench gate 211 are all lined with a gate oxide layer 208 and filled with doped polysilicon. In addition, the third trench gate 211 and the first trench gate 210 have the same depth and width, and at the same time, the spacing between every two adjacent third trench gates is equal or along the same direction. The direction of the edge of the terminal area increases. On the upper part of the N-type epitaxial layer 202 and between every two adjacent first trench gates 210, there is a first P-type body region 204; on the upper part of the N-type epitaxial layer 202 and surrounding Outside the active region, there is a second P-type body region 205. The n+ source region 206 is close to the upper surface of the first P-type body region 204 and close to the sidewall of the first trench gate 210. It is worth noting that the depth of the third trench gate 211 (TFd 1 , TFd 2 , TFd 3 , TFd 4 ……,Such as image 3 Shown) must be greater than or equal to the junction depth of the second P-type body region 205 (Pd, such as image 3 Shown), and there is no n+ source region near the upper surface of the second P-type body region 205, to ensure that the device terminal region has a higher breakdown voltage and prevents large leakage current; at the same time, in this preferred In the embodiment, the depth (Td, such as image 3 (Shown) is greater than the junction depth of the first P-type body region 204. The N-channel trench MOSFET also includes a source body contact trench, a body contact trench, and a gate contact trench. The inner surface of each source-body contact trench is lined with a barrier layer Ti/TiN or Co/TiN or Ta/TiN and filled with a metal tungsten plug 213, and the source-body contact trench penetrates the insulating layer 216 The source region 206 extends into the first P-type body region 204; the inner surface of each body contact trench is lined with a barrier layer Ti/TiN or Co/TiN or Ta/TiN, and is filled with metal Tungsten plug 214, and the body contact trenches pass through the insulating layer 216 and extend into the second P-type body region 205; the inner surface of each gate contact trench is lined with a barrier layer Ti/TiN or Co /TiN or Ta/TiN, and filled with metal tungsten plug 215, and the gate contact trench penetrates the insulating layer 216 and extends into the polysilicon located in the second contact trench 212. Around the bottom of each of the source body contact trenches and the body contact trenches, there is a p+ body contact region 217 to reduce contact resistance. The N-channel trench MOSFET also includes a source metal 220 and a gate metal 222. The source metal 220 is in electrical contact with the source region 206 and the first P-type body region 204 through a tungsten plug 213 and a tungsten plug 214; the gate metal 222 is in contact with the second trench gate The tungsten plug 215 forms electrical contact between 212. As mentioned above, just because there is no n+ source region between every two adjacent third trench gates in the terminal region in this structure, even when the third trench gate is turned on, there will be no Current flows from the drain 200 through the channel region near the third trench gate to the n+ source region 206 in the active region. The cell structure of the N-channel trench MOSFET may be multiple closed cell structures, such as Figure 4 As shown, or multiple ribbon-shaped unit structures, such as Figure 5 Shown.
[0070] Image 6 Shows another preferred embodiment according to the present invention, which is also Figure 4 Top view shown in along Y 1 -Y 2 Cutaway view of direction. Image 6 The structure shown in image 3 The structure shown in is similar, except that in Image 6 Although the width and depth of the third trench gate 311 in the terminal region are the same, they are both larger than the width and depth of the first trench gate 310 in the active region. At the same time, the depth of the first trench gate 310 in the active region is smaller than the junction depth of the first P-type body region 304 to ensure that the device has a higher breakdown voltage and a lower gate-drain charge Qgd in the active region. This is because, such as Figure 7 As shown, when the depth (Td) of the first trench gate in the active region is larger, the breakdown voltage of the active region is smaller and the Qgd is higher. reference Figure 8 As shown in the relationship between the trench depth and the critical dimension of the trench width, it can be seen that the realization of this structure only requires a trench etching process, because when the critical dimension of the third trench gate 311 in the terminal area is greater than For the critical dimension of the first trench gate 310 in the source region, the depth of the third trench gate 311 will inevitably be greater than the depth of the first trench gate 310 during the etching of the same trench.
[0071] Picture 9 Shows another preferred embodiment according to the present invention, the structure and Image 6 The structure shown in is similar, except that in Picture 9 In each of the first trench gate 410, the second trench gate 412, and the bottom of the third trench gate 411, there is an n* doped region 418, and the majority carrier of the n* doped region The concentration is higher than that of the epitaxial layer to further reduce the source and drain resistance Rds.
[0072] Picture 10 Shows another preferred embodiment according to the present invention, the structure and Image 6 The structure shown in is similar, except that in Picture 10 Among them, the depth of the first trench gate 510 located in the active region is greater than the depth of the first P-type body region 504.
[0073] Picture 11 Shows another preferred embodiment according to the present invention, the structure and Picture 10 The structure shown in is similar, except that in Picture 11 , The third trench gate 611 located in the terminal area has different depth and width, however, the depth and width of each third trench gate 611 are respectively greater than those of the first trench gate 610 located in the active area. Depth and width. More preferably, the width of the third trench gate 611 increases in the direction toward the edge of the terminal area (TFw 1 2 3...), which means that the depth of the third trench gate 611 also increases in the direction toward the edge of the terminal region. In another preferred embodiment, the width of the third trench gate 611 decreases in the direction toward the edge of the terminal region (TFw 1TFw 2TFw 3...).
[0074] Picture 12 Shows another preferred embodiment according to the present invention, which is also Figure 13 Top view shown in X 1 -X 2 Cutaway view of direction. Picture 12 The structure shown in Picture 11 The structure shown in is similar, except that in Picture 12 , There is no body contact trench extending into the second P-type body region 705 located between the first trench gate 710 and the adjacent second trench gate 712. Therefore, it is located between the first trench gate and the adjacent The second P-type body region between the second trench gates is not connected to the source region, but has a floating voltage. Picture 12 The cell structure of the trench MOSFET shown can be a closed cell structure, such as Figure 13 Shown, or a ribbon-shaped unit structure, such as Figure 14 Shown.
[0075] Figure 15A~15E Shows manufacturing Picture 10 The process steps of the trench MOSFET shown in. in Figure 15A In the first step, an N-type epitaxial layer 502 is grown on the N+ substrate 500, and then a trench mask (not shown) is provided on the epitaxial layer 502 and dry silicon etching is performed to form a plurality of 502 in the epitaxial layer. Groove. It is worth noting that the width of the trench in the terminal region is greater than the width of the trench in the active region.
[0076] in Figure 15B In the process, a sacrificial oxide layer is first grown and the sacrificial oxide layer is removed to also eliminate silicon defects caused during the etching process. After that, a gate oxide layer 508 is formed on the inner surface of all trenches and the outer surface of the epitaxial layer. Then, on the gate oxide layer 508, doped polysilicon is deposited and subjected to chemical mechanical polishing or plasma The etching is performed back to form a plurality of first trench gates 510 in the active area, at least one wider second trench gate 512 for gate connection, and a plurality of third trench gates 511 in the terminal area .
[0077] in Figure 15C In this step, ion implantation and diffusion of the P-type body region are first performed to form a first P-type body region 504 and a second P-type body region 505 located on the upper portion of the N-type epitaxial layer 502. Then, a layer of source region mask (not shown) is provided, and ion implantation and diffusion of the n + source region are performed to form an n + source region 506 located close to the upper surface of the first P-type body region 504.
[0078] in Figure 15D In this, an insulating oxide layer 516 is deposited on the N-channel trench MOSFET device unit, and then a contact mask (not shown) is provided thereon, and a plurality of contact trenches are formed by etching. Among these contact trenches, the source-body contact trench 513' penetrates the insulating layer 516, the n+ source region 506 and extends into the first P-type body region 504; the body contact trench 514' penetrates all the The insulating layer 516 extends into the second P-type body region 505; the gate contact trench 515' penetrates the insulating layer 516 and extends into the polysilicon region in the second trench gate 512. After that, ion implantation of P-type ions is performed to form a p+ body contact region 517 around the bottom of each of the source-body contact trench 513' and the body contact trench 514'.
[0079] in Figure 15E In, first deposit a layer of Ti/TiN or Co/TiN or Ta/TiN as a barrier layer on the inner surface of all the above-mentioned contact trenches, and then deposit metal tungsten and remove excess parts to form contact trenches located in the source body. The tungsten plug 513 in the groove, the tungsten plug 514 in the body contact trench, and the tungsten plug 515 in the gate contact trench. Then, a resistance reducing layer Ti or Ti/TiN is deposited on the insulating layer 516, the tungsten plug 513, the tungsten plug 514, and the tungsten plug 515, and an Al alloy is deposited on the resistance reducing layer Or a Cu alloy, and a metal mask (not shown) is provided to form the source metal 520 and the gate metal 522.
[0080] Although various embodiments have been described herein, it can be understood that various modifications can be made to the present invention through the above guidance within the scope of the appended claims without departing from the spirit and scope of the present invention. For example, the method of the present invention may be used to form structures of various semiconductor regions whose conductivity types are opposite to those described herein.
