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Integrated circuit structure

A technology of integrated circuits and dielectric materials, which is applied in the field of semiconductor fins and fin field effect transistors and their formation, and can solve problems such as affecting the performance of integrated circuits.

Active Publication Date: 2011-05-25
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Parasitic capacitance adversely affects the performance of respective integrated circuits and needs to be reduced

Method used

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  • Integrated circuit structure
  • Integrated circuit structure
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Embodiment Construction

[0053] Novel methods of forming Fin field-effect transistors (FinFETs) are provided. Intermediate stages in the manufacture of an embodiment are illustrated. Variations of embodiments are discussed. The same reference numerals are used to represent the same elements throughout the different drawings and illustrated embodiments.

[0054] see figure 2 , providing a semiconductor substrate 20 . In one embodiment, the semiconductor substrate 20 includes silicon. Other commonly used materials such as carbon, germanium, gallium, arsenic, nitrogen, indium, and / or phosphorus, and the like may also be included in the semiconductor substrate 20 . The semiconductor substrate 20 can be a bulk substrate or a semiconductor-on-insulator substrate. The semiconductor substrate 20 includes a portion in an intra-device region 100 and a portion in an inter-device region 200 . Each inner device region 100 may be used to form a FinFET, and the inner device regions 100 may be separated from e...

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Abstract

An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a topportion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value. Intra-device shallow trench isolation (STI) regions are formed by using low dielectric constant materials so as to reduce the parasitic gate capacitance of the fin-type field effect transistor and increase the speed of the respective fin-type field effect transistor.

Description

technical field [0001] The present invention relates generally to integrated circuits, and more particularly to semiconductor fins and Fin field-effect transistors (FinFETs) and methods of forming the same. Background technique [0002] With the increasing downsizing of integrated circuits and the increasing high demands on the speed of integrated circuits, transistors must have higher drive currents and smaller and smaller sizes. Finfield-effect transistors (FinFETs) are therefore developed. figure 1 A cross-sectional view of a common FinFET is shown, where the cross-section is fabricated across the fin instead of the source and drain regions. Fin 100 is formed as a vertical silicon fin extending above substrate 102 and used to form source and drain regions (not shown) and a channel region therebetween. Forming the fin 100 includes recessing the substrate 102 to form the recess, filling the recess with a dielectric material, performing a chemical mechanical polish (CMP) t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78H01L27/088H01L21/762
CPCH01L21/845H01L27/0886H01L27/1211H01L21/76224H01L21/76229H01L21/823431H01L29/785
Inventor 袁锋李宗霖陈宏铭张长昀
Owner TAIWAN SEMICON MFG CO LTD
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