Isolating method for silicon mesa vertical channel field effect transistor

Abstract

The present invention provides the isolating process silicon mesa vertical channel FET, and belongs to the field of ultralarge CMOS IC manufacturing technology. The process includes the steps of: the first itching of active region silicon mesa, protecting the surface and side wall of the active region Si mesa with silicon nitride, and subsequent local oxidizing the field area to complete the isolation process. During the subsequent silicon mesa etching in preparing silicon mesa vertical channel device, the active region and the field region are maintained in the same height without step polysilicon side wall in the edges of the active region and the field region, and this reduces the parasitic grid capacitor of silicon mesa vertical channel device and optimizes the DC characteristic and AC characteristic of the device.

Description

technical field [0001] The invention belongs to the technical field of CMOS ultra-large-scale integrated circuit manufacturing, and in particular relates to an isolation process of a silicon mesa type vertical channel field effect transistor. Background technique [0002] With the rapid development of traditional planar CMOS VLSI technology, the feature size of MOS devices has entered the era of submicron and deep submicron (<0.1 micron), but the further reduction of device size will be affected by lithography technology (existing The minimum resolution of the best optical lithography techniques is limited to 0.193 microns). The proposal of the vertical channel field effect transistor has opened up a new way to break through the limitation of photolithography technology and realize the fabrication of deep submicron MOS devices. The working principle of the vertical channel device is exactly the same as that of the planar device, but its drain region, channel region and s...

AI Technical Summary

Problems solved by technology

Referring to Figure 1, in the fabrication of silicon mesa-type vertical channel devices, although the process flow of these two types of isolation processes is very simple, when etching the silicon mesa of the device, it is inevitable that the edge between the active region and the field region Steps are formed at the gate oxide and polysilicon gate sidewalls of the device, a parasitic gate oxide layer and polysilicon gate sidewalls will be formed at the steps at the edge of the active region and field region, and the parasitic polysilicon gate sidewalls and The polysilicon sidewall gates on both sides of the device silicon platform are connected, which introduces a large parasitic gate spacer capacitance

Images