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Process method for packaging semiconductor with exposed pins

A process method and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of high manufacturing cost, long preparation period, and additional design and manufacturing, so as to improve packaging efficiency and reduce The effect of manufacturing cost

Active Publication Date: 2013-11-27
重庆万国半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, using the above packaging method to package semiconductor devices with exposed pins has the following disadvantages: due to the plastic packaging, glue removal, cutting and separation processes involved in the above steps, they all have certain uniqueness in the operation process. For example, in the plastic sealing step, it is necessary to use metal ribs as the separation, and form several plastic sealing cavities on the entire lead frame; A lead frame unit in a plastic package can eventually form several independent semiconductor devices
For these unique process operation requirements mentioned, and for the packaging of different types of semiconductor devices with exposed pins, it is necessary to design and manufacture processing molds or mechanical tools that can meet and realize these process requirements, so that it is impossible Avoided lead to the whole process has a long preparation cycle and high manufacturing costs

Method used

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  • Process method for packaging semiconductor with exposed pins
  • Process method for packaging semiconductor with exposed pins
  • Process method for packaging semiconductor with exposed pins

Examples

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Embodiment 1

[0051] Such as Figure 2A-2F , Figure 3A-3F as well as Figure 4 As shown, it is a specific embodiment of the process method of semiconductor packaging with exposed leads provided by the present invention, which is aimed at packaging and forming semiconductor devices with exposed leads with a lead frame having the following structural features.

[0052] Such as Figure 2A and Figure 3A As shown, the lead frame includes several lead frame units 1 arranged and distributed, and metal ribs 2 for connecting the lead frame units. In order to clearly and concisely display and illustrate the structure of the lead frame, in this embodiment, four lead frame units ( Figure 2A framed by a dotted line) as an example. Wherein, each lead frame unit 1 includes a loading table 11 and several pins 12 located on both sides of the loading table 11; The exposed portion 122 of. Further, the connection between the adjacent lead frame units 1 is realized by connecting the predetermined expo...

Embodiment 2

[0062] Such as Figures 5A-5F , Figures 6A-6F as well as Figure 7 Shown is another specific embodiment of the semiconductor packaging process method with exposed leads provided by the present invention, which is aimed at packaging and forming semiconductor devices with exposed leads with a lead frame having the following structural features.

[0063] Such as Figure 5A and Figure 6A As shown, the lead frame includes several lead frame units 1' arranged in a row and metal ribs 2' for connecting the lead frame units. In order to clearly and concisely display and illustrate the structure of the lead frame, in this embodiment, it also includes 4 lead frame units ( Figure 5A framed by a dotted line) as an example. Wherein, each lead frame unit 1' includes a loading table 11' and several pins 12' located on both sides of the loading table 11'; The exposed portion 122 ′ is predetermined to be exposed outside the plastic package, and the predetermined exposed portion 122 ′ o...

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Abstract

The invention provides a process method for packaging a semiconductor with exposed pins, comprising the following steps: (1) carrying out chip sticking and connection bonding on a lead frame; (2) packaging the whole lead frame into a plastic packaging body; (3) cutting and removing metal ribs and a plastic packaging material above the exposed parts of various pins, thus forming a plurality of plastic packaging strips which are separated by the metal ribs; and (4) carrying out longitudinal rib cutting and horizontal cutting on the lead frame, thus forming a plurality of independent semiconductor packaging devices with the exposed pins. In the process method for packaging the semiconductor with the exposed pins provided by the invention, utilized processing molds and mechanical tools are respectively applicable to a common packaging process and a processes for packing different types of semiconductors with the exposed pins simultaneously, extra design and operating tools such as special molds and the like manufactured are not needed, so that the packaging efficiency is effectively improved, and the manufacturing cost is lowered.

Description

technical field [0001] The invention relates to a semiconductor packaging process, in particular to a packaging process method for semiconductor devices with exposed pins. Background technique [0002] In the prior art, the packaging method of semiconductor devices with exposed pins generally adopts the following process, which specifically includes steps: [0003] Step 1, chip sticking: For each lead frame unit on the lead frame, respectively stick the chip on its carrier stage; wherein, the lead frame includes several lead frame units, and each lead frame unit contains a carrier stage, and a number of pins located on both sides of the stage; adjacent lead frame units are connected by connecting each pin to a metal rib; [0004] Step 2, wire bonding: for each lead frame unit, connect the chips and pins therein with metal wire bonding; [0005] Step 3, plastic packaging: plastic packaging the lead frame, packaging the chip, slide table and some pins in the plastic packagin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/60
CPCH01L2224/32245H01L2224/48091H01L2224/73265H01L2224/48247H01L2224/49111H01L2224/0603H01L2924/181H01L2924/00014H01L2924/00H01L2924/00012
Inventor 薛彦迅鲁军
Owner 重庆万国半导体科技有限公司