Bootstrap sampling circuit

Abstract

The invention provides a bootstrap sampling circuit. The bootstrap sampling circuit comprises a transistor sampling switch; the source of the sampling switch inputs an input signal to be sampled, the drain of the sampling switch outputs a sampled output signal, and the grid of the sampling switch is connected with a bootstrap circuit; the bootstrap circuit drives the sampling switch to switch on and off, and the bootstrap circuit comprises a capacitor charging circuit and a sampling switch starting circuit, wherein the capacitor charging circuit charges a charging capacitor at a first clock signal, and the sampling switch starting circuit starts the sampling switch at a second clock signal; and the grid of the sampling switch is connected with the first end of the charging capacitor through the sampling switch starting circuit, the source of the sampling switch is connected with the sampling signal input end and connected with the second end of the charging capacitor through the sampling switch starting circuit, then the voltage difference of the grid and the source of the sampling switch is the charging voltage of the charging capacitor, and the conduction resistance of the sampling switch is a constant value, so that high linearity sampling is realized.

Description

【Technical field】 [0001] The invention relates to the field of signal acquisition circuits, in particular to a bootstrap sampling circuit using a transistor as a sampling switch. 【Background technique】 [0002] In the circuit that converts analog signal into digital signal, sampling the analog signal is the premise of realizing digitization. In the prior art, a transistor is usually used as a sampling switch, and a control circuit including a charging capacitor is used to control the opening of the sampling switch to implement sampling. [0003] Chinese Patent No. 02131732.1 discloses a sampling circuit using a transistor as a sampling switch. As shown in Figure 2 of the 02131732.1 patent, the switch SW1 is controlled by the clock signal CK. When the clock signal CK is 1, the switch SW1 is closed, so that the potential of the gate G of the PMOS transistor is the preset 2v. The voltage is 2v, no matter what the input voltage is at this time, the PMOS tube is not turned on. ...

AI Technical Summary

Problems solved by technology

[0006] However, the sampling circuit disclosed in U.S. Patent Publication No. 7,397,284 uses a large number of transistors, and the power consumption of the entire circuit will be large, and the circuit area occupied by the integrated circuit is large, and the cost is correspondingly high.

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