Manufacturing methods for dual damascene process and integrated circuit

Abstract

The invention provides manufacturing methods for a dual damascene process and an integrated circuit. The manufacturing method for the dual damascene process comprises: a through hole forming step, in which a through hole is formed by a photomask; a through hole filling step, in which the through hole formed in the through hole forming step is filled by a negative photoresist; a through hole area exposing and developing step, in which a filled through hole area is exposed and developed by the photomask which is the same as a through hole layer after the through hole filling step; and a groove forming step, in which a groove is formed after the through hole filling step. According to the methods, a space of the etched through hole is filled by the negative photoresist with good hole filling performance, so that good filling of the space of the through hole is guaranteed, the good flatness of a surface of a silicon wafer is recovered, and the appearance of an oblique etched face of the etched groove is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing technology, in particular to an improved double damascene manufacturing method and an integrated circuit manufacturing method using the double damascene manufacturing method. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, the volume of semiconductor devices is becoming smaller and smaller, making the resistance and parasitic capacitance between metals also increasing. For microprocessors, the limitation of chip speed is mainly caused by the resistance and parasitic capacitance in the plating layer. As a result, problems such as resistance-capacitance time delay, mutual interference between signals and energy loss have become increasingly prominent. [0003] In order to solve the problem of resistance-capacitance time delay, in terms of resistance, in the past 30 years, the semiconductor industry has used alumin...

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Problems solved by technology

The difficulty encountered in this mainstream approach is that after the through-hole etching, the area where the through-hole area is located needs to be filled with anti-etching materials to achieve optimal surface flatness. There are two main methods, one is direct spin coating filling Material, the disadvantage of this method is that after spin coating, the thickness of the filling material in the via area is always smaller than that of the non-via area, and the filling material where the via is located will form a pit shape, which will cause etching In the process, after the anti-reflection layer is etched, the filling material in the via hole area drops, and cannot protect the tops on both sides of the via hole, so that the sloped facets formed on the top of the via hole ( figure 1 It shows the difference in morphology after etching in different areas caused by this process); another way to smooth the surface is to add a back-etching process after multiple spin-coating filling materials to reduce the thickness of the filling material and shrink the size of the filling material. The thickness of the filling material in the through-hole area and the non-through-hole area is different. The disadvantage of this method is that multiple times of spin-coating the filling material will take up a lot of time for the lithography machine, and an additional etching process will be added, which will affect the overall production of the production line. The ratio has a great influence, and this method itself cannot completely solve the problem of slope facet after trench etching caused by thickness difference

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