MOS (Metal Oxide Semiconductor) field effect transistor

Abstract

The invention provides an MOS (Metal Oxide Semiconductor) field effect transistor comprising a substrate, a source electrode, a drain electrode and a grid stack, wherein the source electrode and the drain electrode are formed in the substrate; the grid stack is formed above the substrate and positioned between the source electrode and the drain electrode; and a grid dielectric layer is made of a dielectric material with an adjustable K value. In the embodiment of the invention, the dielectric material with the adjustable K value is applied to the grid dielectric layer of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device; the grid capacitance is increased by dynamically obtaining the high K value; and the capability of the CMOS device on controlling the short channel effect and the switching rate are improved.

Description

technical field [0001] The invention relates to the field of semiconductor design, in particular to the structure of a MOS field effect transistor (MOSFET). Background technique [0002] With the continuous development of semiconductor technology, the feature size of CMOS devices continues to shrink, which causes problems such as short channel effects. Using high dielectric constant (K value) materials (such as HfSiON, HfAlON, etc.) to replace SiO2 to make gate dielectric layers can be used. The current of the device is increased, the driving ability of the device is enhanced, the ability to control the short channel effect is improved, and the further reduction of the device is possible. Existing integrated circuit devices all use dielectric materials with a fixed K value as the gate insulating medium. However, from the perspective of AC performance of the device, not all areas of the gate insulating medium are as high as possible. For example, when a CMOS device is in an ...

AI Technical Summary

Problems solved by technology

Due to the above considerations, many device optimization research and development and patents adopt asymmetric device structure (asymmetric device structure), but asymmetric devices usually require additional lithography masks, which increases the cost, and the process itself is also subject to various constraints. Various constraints (such as the angle of ion implantation, the height and distance of the grid, etc.)

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