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64results about How to "Increase K value" patented technology

Active reconfiguration strategy of distribution network and preventing control method thereof

The present invention relates to a safe operation and prevention control technique of an active distribution network, wherein preventive control is performed through optimizing a network structure for satisfying a safe margin requirement in operation of the distribution network, thereby effectively improving operation reliability of the distribution network; and simultaneously operation and short-term planning of the distribution network are guided for realizing higher economic benefit and social benefit. For this purpose, the technical solution adopted in the active reconfiguration strategy of the invention is characterized in that the active reconfiguration strategy of the distribution network and the preventing control method comprise the steps of: firstly, establishing a maximal power supply capability evaluating index which is adapted for the active distribution network; when the maximal power supply capability index of the distribution network is lower than a system safe guard line, performing active reconfiguration of the distribution network for achieving multiple targets of improving the maximal power supply capability index and minimizing number of times of operating a network reconfiguration switch; and if the maximal power supply capability index of the distribution network in the current operation manner is lower than a preset safe guard line, starting an active reconfiguration module for performing network optimizing reconfiguration. The active reconfiguration strategy of the distribution network and the preventing control method according to the invention are mainly applied for safe operation and preventing control of the distribution network.
Owner:TIANJIN UNIV

Method for calibrating small-diameter probe for ultrasonic flaw detector

The invention discloses a method for calibrating a small-diameter probe for an ultrasonic flaw detector, belonging to the method for calibrating an instrument. The method for calibrating the small-diameter probe for the ultrasonic flaw detector comprises the following steps in sequence: manufacturing a test block for calibrating the small-diameter probe for the ultrasonic flaw detector; moving the external circular arc probe near the point O1 on the surface of the arc of the test block back and force, wherein the arc of the test block is drawn by adopting the radius R2; obtaining the range S1 of the echo of a radius R1; measuring the distance between the point O1 and the foremost edge of the small-diameter probe, wherein the distance is the front edge b of the small-diameter probe; adjusting the direction of the small-diameter probe to make the small-diameter probe aligned to the direction of the hole, and obtaining the range S of the echo of the hole; and obtaining the range a of the echo in the small-diameter probe and the value K of the small-diameter probe. The invention makes up the blank of the calibration of the value K of the small-diameter probe, the front edge b of small-diameter probe and the range a of the echo in the small-diameter probe and reduces the loss cost of the small-diameter probe.
Owner:符丰

Ventilation and heat preservation module heating and cooling floor and energy-saving ventilation and air conditioning system

InactiveCN104763087AReduce energy consumptionImprove the effect of ventilation and air conditioningDucting arrangementsHot-air central heatingFresh airEngineering
The invention relates to a ventilation and heat preservation module heating and cooling floor and energy-saving ventilation and air conditioning system which comprises a ventilation and heat preservation module heating and cooling floor body, a ventilation and air conditioning system body and a heat preservation and ventilation window. The ventilation and heat preservation module heating and cooling floor body is composed of an expandable polyethylene cushion layer, a ventilation and heat preservation module body, a floor heating pipeline, a water division and collection device, a dehumidification and heat radiation air supply pipe, a dehumidification and heat radiation air channel, a dehumidification and heat radiation air collection pipe, an air conditioner floor air supply pipe, a dampproof heat conduction layer and a wood floor from bottom to top in sequence. The heat preservation and ventilation window and the ventilation and air conditioning system body are communicated to form the complete energy-saving ventilation and air conditioning system. The K value of the window is improved, the heat preservation and ventilation window is adopted as an air inlet and exhaust channel, and the energy consumption of a ventilation air conditioner is lowered. The effect of the ventilation air conditioner is improved, a floor heating tail end has the two purposes for heating and cooling, waste heat is recycled, and mounting and running cost is lowered. The aims that air is purified, and a user can breathe clean and fresh air without opening the window are achieved.
Owner:冯刚克

SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL)

The invention relates to an SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL). The method includes the following steps of utilizing a Kripke structure to describe a system model M to be verified; utilizing a PPTL formula to describe a property P; setting up a bound k; converting the bounded model checking for the PPTL into an SAT problem; and solving the SAT problem. In the step of solving the SAT problem, a solution of the SAT problem indicates that the system model M is not satisfiable to the property P, otherwise, non-solution of the SAT problem indicates that the bound of the system model M is satisfiable to the property P; the value of the K is increased to move on to the next checking period until the value of the k is large enough and the bound of the system model M is satisfiable to the property P in every bounded model checking period. The problem that a CTL (computation tree logic) and an LTL (linear temporal logic) are limited in abilities of expression is solved by utilizing the PPTL to describe the system property, the status space explosion problem is released by limiting searching length to reduce searching status number, and convenience and effectiveness for checking complex system property are improved by combining respective advantages of the PPTL and the BMC. The SAT based method for the bounded model checking for the PPTL is applicable to formal verifications for soft and hardware systems and communication protocols.
Owner:XIDIAN UNIV

Preparation method of high k-gate dielectric layer and silicon carbide MOS power device

The present invention provides a preparation method of a high k-gate dielectric layer and a silicon carbide MOS power device. The preparation method comprises the steps of: performing high-temperaturesacrificial oxidation of a silicon carbide epitaxial wafer with a first conductive type, and forming a sacrificial oxidation layer at the upper surface of the epitaxial layer of the silicon carbide epitaxial wafer; performing corrosion of the sacrificial oxidation layer until the sacrificial oxidation layer on the epitaxial layer is completely removed; performing high-temperature surfacing processing of the upper surface of the epitaxial layer after removal of the sacrificial oxidation layer, and forming a smooth passivated surface; and depositing an Al2O3 dielectric coating layer, a LaAlO3 dielectric layer and an Al2O3 dielectric coating layer at the smooth passivated surface in order, performing annealing of a laminated structure formed by the Al2O3 dielectric coating layer, the LaAlO3dielectric layer and the Al2O3 dielectric coating layer, and forming a high k-gate dielectric layer. Compared to the prior art, the preparation method of the high k-gate dielectric layer and the silicon carbide MOS power device can reduce the interface defects caused by impurities and/or surface lattice defects at a SiC/SiO2 interface so as to improve the voltage endurance capability of the gate dielectric layer.
Owner:GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2

Production method of metal-silicon nitride-metal capacitor

The invention provides a production method of a metal-silicon nitride-metal capacitor, which comprises the steps of: 1) depositing a low-k-value dielectric layer; 2) forming a metal-oxide-metal (MOM) area through photoetching and etching; 3) depositing high-k-value silicon nitride through a plasma enhanced chemical vapor deposition (PECVD) method; 4) removing excessive silicon nitride through chemical and mechanical grinding to form a low-k-value dielectric and silicon nitride mixed layer; 5) completing photoetching and etching to form a metal groove on the low-k-value dielectric and silicon nitride; 6) completing the deposition and the chemical and mechanical grinding of the metal layer and then forming the metal fillers of a conducting wire and an MOM capacitor; and 7) completing copper interconnection and the production of the MOM capacitor. By improving the k value of the dielectric of the inter-layer capacitor, the capacitance of the inter-layer capacitor is effectively improved. By improving the performance of the high-k-value silicon nitride, the electric properties such as the puncture voltage, the leakage current and the like of the MOM capacitor and the electric uniformity of devices are effectively improved. The production method is very practical.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP

Method for producing multilayer metal-silicon nitride-metal capacitor

The invention provides a method for producing a multilayer metal-silicon nitride-metal capacitor, which includes the following steps: 1) using a plasma enhanced chemical vapor deposition (PECVD) method to deposit a silicon nitride thin film with a high k value on a silicon chip substrate; 2) removing silicon nitride in a non-metal-oxide-metal area through photoetching and etching; 3) depositing a dielectric layer with a low k value; 4) removing redundant silicon nitride through chemical mechanical polishing, and forming a mixing layer of low-k-value dielectric and silicon nitride; 5) completing photoetching and etching to form a metallic channel in the low-k-value dielectric and the silicon nitride; 6) forming metal fillers of a lead and a metal-oxide-metal (MOM) capacitor after deposition and chemical mechanical polishing of a metal layer are completed; and 7) repeating Step 1) to Step 6) to form multilayer MOM capacitor. The method for producing the multilayer metal-silicon nitride-metal capacitor can effectively improve the capacitance of the interlayer capacitor, can also effectively improve various electric characteristics of the MOM capacitor such as breakdown voltage, leakage current and the like, can effectively improve electric uniformity among various apparatuses, and is very practical.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP

A method for reducing the k value of the dielectric material between vias in the back-end copper interconnection process

The invention provides a method for lowering k value of a dielectric material among through holes in a back end copper interconnect process. After deposition of a barrier layer, a silicon oxide film is deposited; before deposition of a low-k dielectric material, a silicon oxide film in a non through hole area is etched, and a silicon oxide film in a through hole area is reserved, so that in following process of etching of through holes, a slope is formed on a side wall of the silicon oxide film as the silicon oxide film is hard and has a low etching rate, another slope is also formed on a side wall of the barrier layer, and the two slopes jointly form a through hole slope. Compared with the through hole slopes prepared by conventional technologies, the through hole slope prepared by the method is increased in height and angle, so that electric leakage caused by breakdown of a metal piece due to too small corner cut of the through holes is prevented; furthermore, the k value of the dielectric material among the through holes is increased as the bottom of the low-k dielectric material has silicon oxide and nitrogen doped silicon carbide in the prior art, however, the k value can be reduced by adopting the method.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP
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