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SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL)

A technology of projected sequential logic and model detection, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of model detection method state space explosion, limited expression ability, etc., to achieve the effect of easy verification and improved efficiency

Active Publication Date: 2012-09-12
XIDIAN UNIV
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Problems solved by technology

[0006] Due to the limited expression ability of CTL and LTL, the model checking method also has the problem of state space explosion, and there is no solution to these two problems at the same time in the existing technology, so a method that can effectively solve these two problems at the same time is proposed. method without delay

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  • SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL)
  • SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL)
  • SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL)

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Embodiment 1

[0051] The invention is a SAT-based propositional projection temporal logic boundary model detection method, which uses the specification description language PPTL with regular expression ability to describe the properties of the system to be verified, and verifies the properties of the system to be verified through the detection method of the boundary model. During the verification process In this paper, the problem of bounded model detection is transformed into a SAT problem, and the solution of the SAT problem is used to judge whether the system to be verified is bounded and satisfies the property. The system to be verified is either a newly developed software system, or a newly developed hardware system, or a communication protocol, or an algorithm. The properties of the system to be verified are either safety-related or activity-related. The design and development process of these systems often need to expend huge manpower and material resources, therefore, before these n...

Embodiment 2

[0081] SAT-based propositional projection temporal logic boundary model detection method is the same as embodiment 1, such as figure 1 Shown, the present invention is described from another angle, and the present invention mainly comprises the following parts:

[0082] 1. System modeling

[0083] Analyze the system to be verified and establish a corresponding system model. During the modeling process, the system needs to be abstracted to a certain extent, and the established model should faithfully reflect the behavior of the system, and the scale should be compact. The invention establishes the Kripke structure model of the finite state transition system for the system to be verified. Firstly, the definition of the Kripke structure of the finite state transition system is given:

[0084] The Kripke structure M is a quadruple M=(S, I, T, L), where S is a finite state set; is the initial state set; is a set of transition relations, and conforms to the complete relation, ...

Embodiment 3

[0105] The SAT-based propositional projection temporal logic boundary model detection method is the same as that in Embodiment 1-2.

[0106] In a communication system, there are often situations where multiple users apply for the right to use the same channel at the same time, but the system will only authorize one user to use the channel at the same time. This is a typical shared resource allocation problem. Assuming that two users apply for the right to use the same channel at the same time, it can be modeled as a mutual exclusion system with two independent processes applying for a critical resource at the same time. The system M is a mutually exclusive system with two processes, and a Kripke structure model is established for M, such as Figure 4 (a), where x indicates that process A is in the critical section, and y indicates that process B is in the critical section. Consider the property P of the system: "neither process A nor process B is in the critical section" is a...

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Abstract

The invention relates to an SAT (satisfiability) based method for bounded model checking (BMC) for propositional projection temporal logic (PPTL). The method includes the following steps of utilizing a Kripke structure to describe a system model M to be verified; utilizing a PPTL formula to describe a property P; setting up a bound k; converting the bounded model checking for the PPTL into an SAT problem; and solving the SAT problem. In the step of solving the SAT problem, a solution of the SAT problem indicates that the system model M is not satisfiable to the property P, otherwise, non-solution of the SAT problem indicates that the bound of the system model M is satisfiable to the property P; the value of the K is increased to move on to the next checking period until the value of the k is large enough and the bound of the system model M is satisfiable to the property P in every bounded model checking period. The problem that a CTL (computation tree logic) and an LTL (linear temporal logic) are limited in abilities of expression is solved by utilizing the PPTL to describe the system property, the status space explosion problem is released by limiting searching length to reduce searching status number, and convenience and effectiveness for checking complex system property are improved by combining respective advantages of the PPTL and the BMC. The SAT based method for the bounded model checking for the PPTL is applicable to formal verifications for soft and hardware systems and communication protocols.

Description

technical field [0001] The invention belongs to the technical field of computer applications, mainly relates to the technical field of system formal verification, and in particular relates to propositional projection temporal logic (PPTL) and bounded model detection (BMC), specifically a method for detecting bounded model of propositional projection temporal logic based on SAT. It is mainly used in the formal verification of the correctness of software and hardware systems designed in the fields of industry, military, agriculture, scientific research, etc., as well as the formal verification of the security and reliability of various communication protocols. technical background [0002] With the development of the Internet and the continuous improvement of the needs of the industry, the design complexity of various computer application software and hardware circuits is increasing day by day, and the network communication technology is also changing with each passing day. The...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 段振华何佳田聪王小兵
Owner XIDIAN UNIV
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