Timing processing method and circuit for synchronous static random accessible memory (SRAM)

Abstract

A timing processing method and circuit for synchronous Static Random Accessible Memory (SRAM) is disclosed. The method comprises: inputting address signals to a word line decoder directly to perform logic decoding; generating each signal by means of settings in timing for each device, and performing sensitivity amplification on data inputted from a memory cell array and selected by bit lines and outputting the data afterwards, i.e. generating a data output signal. The synchronous SRAM circuit comprises a word line decoder, a timing generator, a word line controller, a word line pulse width generator, a memory cell array and a sense amplifier.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a timing processing method and circuit of a synchronous SRAM. Background technique [0002] Static Random Accessible Memory (SRAM) is very helpful to improve system performance because it can save the data stored in it without refreshing the circuit. The first-level and second-level caches in the central processing unit (CPU, Central Processing Unit) use SRAM. In order to further improve the performance of the CPU, it is necessary to reduce the timing path of the CPU and integrate small-capacity external first-level or second-level caches. Level SRAM cache, and the timing path of SRAM is one of the critical timing paths, which limits the increase of the operating frequency of the CPU. SRAM can be divided into two categories from a high level: synchronous and asynchronous. Synchronous SRAMs use an input clock to initiate all data transactions (eg, read, write, deselect, etc....

AI Technical Summary

Problems solved by technology

Because the address latch will consume a certain amount of time to latch the address, this increases the timing path running time of the synchronous SRAM and reduces the working speed of the synchronous SRAM.

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