Method for real-time synthesis of image data output by high-resolution multi-tap planar array CCD (Charge Coupled Device)

Abstract

The invention discloses a method for real-time synthesis of image data output by a high-resolution multi-tap planar array CCD (Charge Coupled Device), relating to an image data synthesis method and solving the problem that a line of data in the traditional SDRAM (Synchronous Dynamic Random Access Memory) is read or written by multiple burst operations and multiple judgments on whether to carry out refreshing operation as well as storage activation and pre-charge operation. The method comprises the steps of: dividing image data output by multiple taps of the CCD into four groups and sending todouble-port RAMs of a ping-pong structure for data integration; writing data in the upper left and the lower left double-port RAMs of the ping-pong structure into a left SDRAM of the ping-pong structure, and writing data in the upper right and the lower right double-port RAMs of the ping-pong structure into a right SDRAM of the ping-pong structure; and reading the image data from the left SDRAM of the ping-pong structure and the right SDRAM of the ping-pong structure, respectively sending the image data into a left asynchronous FIFO (First Input First Output) and a right asynchronous FIFO andoutputting the image data. In the invention different refreshing methods are adopted and the operation efficiency for reading and writing is enhanced.

Description

technical field [0001] The invention relates to a method for image data synthesis, in particular to a high-resolution (up to 10K×10K) multi-tap (the number of taps is greater than four and an integer multiple of four) short blanking period area array CCD output image data method for real-time synthesis. Background technique [0002] For high-speed area array CCD sensors, in order to output image signals in a very short time, it is necessary to increase the frame transfer rate and pixel clock, which brings great difficulties to the chip manufacturing process and the design of peripheral drive circuits, and the signal-to-noise ratio will also decrease. deterioration. To alleviate this situation, chip manufacturers adopt multi-tap output design, such as figure 1 As shown, the photosensitive area and storage area of ​​the CCD are divided into multiple blocks, each block has its own output clock, and multiple ports are output in parallel, which greatly reduces the frame transfe...

AI Technical Summary

Problems solved by technology

This method can facilitate the coordination of read and write operations and timing refresh, but for high-resolution image data, the number of columns in the memory is large, and the read and write operations of a row of data need to be completed by multiple burst operations, and multiple judgments are required. Refresh operation and memory activation and pre-flush operation, the controller has a large overhead, low read and write efficiency, and it is difficult to adapt to the operation of image data with high resolution and short blanking period

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