Unlock instant, AI-driven research and patent intelligence for your innovation.

Spacer formation in the fabrication of planar bipolar transistors

A technology of bipolar transistors and spacers, which is applied in the fields of transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of no contribution to device operation and reduction of the width and size of the emitter window.

Active Publication Date: 2014-11-05
NXP BV
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However increasing the width d of the spacer 10 at the top 2 resulting in the width d of the spacer 10 at the bottom 5 increases, which in turn results in the emitter window width dimension W E decreases, and results in increased base link resistance (i.e., a longer base current path under the spacer 10) and higher extrinsic base-collector capacitance, i.e., no contribution to device operation The larger B-C junction of

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Spacer formation in the fabrication of planar bipolar transistors
  • Spacer formation in the fabrication of planar bipolar transistors
  • Spacer formation in the fabrication of planar bipolar transistors

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029]The inventors have realized that it is advantageous to provide a spacer separating the base and emitter portions of a transistor where the top of the spacer is at least as wide as the bottom of the spacer is wide. More preferably, it is advantageous to provide such a spacer which is wider at the top of the spacer than at the bottom of the spacer. Various process techniques for forming such spacers are now described.

[0030] Throughout this specification, including the description, drawings, claims and abstract, the words "collector", "base" and "emitter" (or "collector region", "base region" and "emitter region") Used to facilitate defining the following respectively: (i) a first region in the semiconductor substrate that provides a first dopant level and a dopant type; (ii) disposed on the substrate a second semiconductor region having a second dopant level and a second dopant type to form a junction with the first region; and (iii) disposed on the second region a th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a r-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

Description

technical field [0001] The present invention relates to a planar bipolar transistor, in particular, but not exclusively, to the fabrication of a heterojunction bipolar transistor, for example using a low complexity SiGe:C structure. Background technique [0002] figure 1 A schematic diagram of a conventional planar low-complexity heterojunction bipolar transistor (HBT) is shown. Semiconductor substrate 1 serves as collector region 2 surrounded by shallow trench isolation (STI) regions 3 . A polysilicon gate 4 provides electrical connection to the base epitaxial layer 6 via a polysilicon base stack 7 . The base stack 7 is a vertical part of the base semiconductor region. The polysilicon gate layer 4 is separated from the STI region and the substrate 1 by a gate oxide layer 5 . The emitter 8 has an emitter window width W E The emitter window is in contact with the base. The emitter 8 is further electrically isolated from the base epitaxial layer 6 and the polysilicon bas...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/331H01L29/73H01L29/737H01L29/06
CPCH01L29/66318H01L29/66242H01L29/0817H01L29/20
Inventor 约翰内斯·J·T·M·唐克斯托尼·范胡克汉斯·莫腾斯菲利普·默尼耶-贝拉德
Owner NXP BV
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com