Memory chip bit line failure analysis method

Abstract

The invention provides a memory chip bit line failure analysis method, which comprises the following steps of: performing mechanical grinding to remove most of an interconnect metal layer and a bit line layer of a chip to be analyzed; performing the mechanical grinding to remove most of a substrate of the chip to be analyzed; performing wet etching to completely remove the residual substrate of the chip to be analyzed; performing dry etching to remove most of a dielectric layer at the bottom of a bit line contact window of the chip to be analyzed and retain a thin dielectric layer; and detecting the top of the bit line contact window of the chip to be analyzed to determine the specific position of a bit line failure. By the method, the chip to be analyzed can be fully thinned, the specific position of the bit line short-circuit failure of the chip to be analyzed can be observed and determined directly by an electronic microscope, the working efficiency is greatly improved and time cost is saved.

Description

technical field [0001] The invention relates to the field of semiconductor failure analysis, in particular to a memory chip bit line failure analysis method. Background technique [0002] For mass production of semiconductor devices, failure analysis of designed and manufactured semiconductor devices is an important means to increase yield and improve process technology reliability and stability. [0003] For semiconductor memory devices, a short circuit between bit lines is a common failure condition. A short circuit on a bit line will cause all memory cells on the two bit lines to lose their function, reducing the storage capacity of the memory chip. Therefore, for semiconductor Bit line failure analysis of memory devices is very important. Figure 1a with Figure 1b , are a simplified schematic diagram of a cross-sectional structure of a memory chip with a short circuit in a bit line and a partially enlarged view thereof, respectively. Such as Figure 1a with Figure 1...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a memory chip bit line failure analysis method to solve the problem that the existing bit line failure analysis method cannot quickly find out the exact location of the bit line short circuit

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