In-situ resistance measurement for magnetic random access memory (MRAM)

Abstract

A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.

Description

technical field [0001] The present invention relates to integrated electronic circuits, and in particular to in situ measurement of integrated circuit memory elements. Background technique [0002] In magnetoresistive RAM (MRAM), data is stored as magnetic polarization in elements called magnetic tunnel junctions (MTJs). The resistance depends on the relative polarization of the two layers in the MTJ. One layer is the permanent ("fixed") layer, while the other ("free") layer will change to match the polarization of a sufficiently strong external field. By measuring the resistance, the free layer polarization can be determined. A memory device can be built from a grid of such "cells" incorporating MTJs. [0003] Alternatively, spin-transfer torque (STT) MRAM uses spin-aligned ("polarized") electrons of sufficient critical current density to twist directly and "write" the polarization into the free layer, where the polarization direction and junction resistance Depends on ...

AI Technical Summary

Problems solved by technology

Larger parasitic resistance attenuates the change in measured voltage between the two resistive states of the MTJ (as described above), which attenuation can limit the margin for setting the resistive reference level with In order to distinguish which state the MTJ is in, that is, the resistance is lower than the reference level (R p with R ap average value) is still higher than the reference level

[0010] In addition, the ATE, the cables used to interface the ATE with the memory chip, and the on-chip interconnects can introduce additional parasitic resistance and reactive impedance

These parasitic resistances can be significant compared to the impedance of nanoscale MTJ MRAM devices, and this can limit the accuracy and speed of testing

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