A clock synchronization method and device

Abstract

The embodiments of the present invention disclose a method and apparatus for clock synchronization. The method includes the steps of: a slave clock device simultaneously performing protocol message interaction with multiple clock source devices, and respectively calculating time and frequency offsets from each clock source device according to the protocol message interaction with the multiple clock source devices to lock the multiple clock source devices; and the slave clock device selecting a master clock source from the multiple clock source devices, and correcting the time and frequency of its own using the time and frequency offsets from the master clock source. In the embodiments of the present invention, the clock source device is immediately locked as soon as it is discovered, rather than after the switching, so that the multi-path clock source devices are locked simultaneously by the slave clock device, and when the switching of the clock source device occurs, switching to the currently locked clock source device can ensure the synchronization accuracy of the time and frequency during switching to the maximum extent, accelerate the switching speed of the clock source device, and enhance the switching performance.

Description

technical field [0001] The invention relates to a 1588 clock synchronization protocol, in particular to a clock synchronization method and device. Background technique [0002] Precision Time Protocol (Precision Time Protocol, PTP) IEEE STD1588 is one of the important technologies in the field of time and frequency synchronization control. The 1588 protocol stipulates that the slave clock device simultaneously records five effective clock source devices as alternative sources. The best preferred source is selected by the best clock algorithm (Best Master Clock Algorithm, BMC) as the main clock source of the current system, and the slave clock device performs protocol interaction with the preferred source, calculates the time and frequency deviation and corrects the slave The time and frequency of the clock device. When the preferred source fails, switch to the sub-priority source calculated by the BMC algorithm among the alternative sources, and then restart the protocol i...

AI Technical Summary

Problems solved by technology

[0003] In the actual network application, there are the following problems: when the slave clock device follows the preferred source according to the protocol, it needs to accumulate PDV (network delay jitter) change data for a period of time in order to correctly calculate and filter the PDV of the current link

[0004] During the period from link switching to re-locking the clock source, the time and frequency jitter output from the clock device has a larger deviation than that in the locking case, and the frequency and time synchronization performance is poor.

Images