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Silicon on insulator (SOI) bulk resistor modeling method

A modeling method and volume resistance technology, applied in electrical digital data processing, instruments, calculations, etc., can solve the problem that the volume resistance model is irrelevant to voltage bias, and achieve the effect of reliable and accurate circuit simulation.

Active Publication Date: 2014-05-14
中科瑞测(天津)科技有限公司
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  • Summary
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  • Description
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Problems solved by technology

However, in fact, the voltage bias of the device has a great influence on the bulk resistance, but this is not reflected in BSIM SOI. The present invention is created to solve the problem that the current bulk resistance model has nothing to do with the voltage bias.

Method used

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  • Silicon on insulator (SOI) bulk resistor modeling method
  • Silicon on insulator (SOI) bulk resistor modeling method
  • Silicon on insulator (SOI) bulk resistor modeling method

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Embodiment Construction

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the SOI bulk resistance modeling method provided by the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0025] Such as figure 1 as shown, figure 1 It is a flow chart of a method for modeling SOI bulk resistance provided by the present invention, and the method includes the following steps:

[0026] Step 1: Calculate the cross-sectional area of ​​the neutral body region;

[0027] Step 2: Establish a preliminary model of SOI bulk resistance according to the cross-sectional area of ​​the neutral body region;

[0028] Step 3: Optimizing the preliminary model of SOI bulk resistance to form the final SOI bulk resistance model.

[0029] Wherein, the calculation of the cross-sectional area of ​​the neutral body region in step 1 is to first calculate the width Xdf, Xdb, a1 and ...

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Abstract

The invention discloses a silicon on insulator (SOI) bulk resistor modeling method. The method comprises the following steps: 1. computing the sectional area of a neutral bulk zone; 2. building a preliminary SOI bulk resistor model according to the sectional area of the neutral bulk zone; and 3. optimizing the preliminary SOI bulk resistor model to form a final SOI bulk resistor model. The method has the following beneficial effects: accurate computation of the bulk resistor is realized and the impact of voltage offset on the bulk resistor is reflected, so that the device is simulated more accurately, thus ensuring the more reliable simulation result of the circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductor device modeling, in particular to a method for modeling SOI bulk resistance. Background technique [0002] Since the SOI CMOS circuit achieves complete dielectric isolation, the pn junction area is small, and there is no parasitic field MOS transistor and thyristor structure in the bulk silicon CMOS technology, the photocurrent generated by radiation can be nearly three times smaller than that of the bulk silicon CMOS circuit. An order of magnitude makes SOI circuits have outstanding advantages in anti-single event events and instantaneous radiation. However, due to the existence of the BOX (buried oxide) layer, SOI has a floating area, which will produce a floating body effect. Floating body effects can cause warpage effects, parasitic bipolar transistor effects, abnormal subthreshold slopes, device threshold voltage shifts, and more. [0003] In order to solve this problem, there are gen...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 卜建辉毕津顺韩郑生
Owner 中科瑞测(天津)科技有限公司
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