High-speed data acquisition card implemented on basis of hardware

A technology of high-speed data acquisition and hardware implementation, which is applied in the field of data acquisition cards, can solve problems such as poor positioning accuracy, lack of real-time processing, and unsuitability for real-time detection, and achieve strong anti-interference ability, high acquisition accuracy, and good application value and market value effects

Inactive Publication Date: 2012-02-01
CHINA ELECTRIC POWER RES INST +1
View PDF5 Cites 33 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Of course, there are also many that use FPGA as a controller, but at present, most of them only use FPGA as address control or simple logic control, and there are no real-time processing.
The frequency of the A / D chip used in the domestic acquisition system is usually below 60M, and the resolution is mostly 8 bits, rarely 12 bits; even the data acquisition frequency of the monitoring equipment used for partial discharge can only reach 20M Left and right, this kind of acquisition card is suitable for general or medium-speed applications. For instruments such as partial discharge and corona current measurement, the positioning accuracy will be poor due to the speed, so it is not suitable for real-time detection.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-speed data acquisition card implemented on basis of hardware
  • High-speed data acquisition card implemented on basis of hardware
  • High-speed data acquisition card implemented on basis of hardware

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0016] The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0017] Such as figure 1 , figure 2 As shown, the present invention includes a signal conditioning circuit 1 , an ADC conversion circuit (analog-to-digital conversion circuit) 2 , an FPGA (programmable gate array) data processor 3 , an ARM control module 4 and a power supply 5 .

[0018] The signal conditioning circuit 1 is composed of a digital gain amplifier 6 and a single-ended to differential converter 7. After the signal conditioning circuit 1 receives the test start signal TRIG, the input signal is sequentially converted into The differential signal is then input into the ADC conversion circuit 2 . Wherein, the operation of the digital gain amplifier 6 is controlled by the ADC conversion circuit 2 .

[0019] The ADC conversion circuit 2 collects the input signal under the control of the external clock signal and the sampling clock input signa...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a high-speed data acquisition card implemented on the basis of a hardware, which comprises a signal conditioning circuit. The signal conditioning circuit consists of a digital gain amplifier and a single ended to differential converter, and is used for inputting an input signal into an analog-to-digital conversion circuit sequentially by the digital gain amplifier and the single ended to differential converter; the analog-to-digital conversion circuit is controlled by a sampling clock signal to acquire the input signal, convert the input signal into a digital signal and input the digital signal into an FPGA (Field Programmable Gata Array) data processor; the FPGA data processor is used for carrying out data buffering on the received digital signal and storing digital signal data into a high-speed dynamic memory controlled by the FPGA data processor; the data is transferred onto a PC (Personal Computer) machine by the cooperative work of an on-chip embedded system in which the FPGA data processor is used as the core and an ARM (Advanced RISC Machines) control module; and a power supply comprises an analog power supply network and a digital power supply network and has an external power supply mode. After the high-speed data acquisition card is adopted, 500MHz analog-to-digital sampling and real-time storing functions can be realized. The high-speed data acquisition card can be widely applied to the field of acquisition of the high-speed signal data.

Description

technical field [0001] The invention relates to a data acquisition card, in particular to a hardware-based high-speed data acquisition card used in the field of high-speed signal data acquisition in electric power systems. Background technique [0002] At present, ultra-high-speed data acquisition boards are mainly used in ultra-high-speed signal acquisition occasions, SAR (Synthetic Aperture Radar) signal echo acquisition, radar signal reconnaissance and reception, storage frequency interference, software radio, etc. that require ultra-wideband. Under the data acquisition rate of GSPS, I / Q channel synchronization, various trigger modes, real-time storage of data, preprocessing and transmission of collected data, and clock network distribution become very difficult to realize. Most of the existing data acquisition boards have a sampling rate below 250MSPS and a bandwidth of tens of MHz. These acquisition boards cannot cope with the current broadband signals of hundreds of MH...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/40
Inventor 刘元庆杨庆华刘颖异袁海文陆家榆崔勇
Owner CHINA ELECTRIC POWER RES INST
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products