Chemical mechanical grinding method and chemical mechanical grinding system

Abstract

Embodiments of the invention provide a chemical mechanical grinding method and a chemical mechanical grinding system. The invention is used for chemically and mechanically grinding a silicon oxide insulating layer when tungsten is chemically and mechanically ground. The method comprises the steps of: providing a first batch of wafers, wherein each wafer comprises an insulating layer and a tungsten metal layer embedded in the insulating layer; grinding the insulating layer of a first wafer in the first batch of wafers to obtain the grinding thickness of the insulating layer of the first wafer; comparing the grinding thickness with a preset target thickness value so as to obtain a corrected value of the grinding time; and grinding the residual wafers in the first batch of wafers by adopting the corrected value of the grinding time. The embodiments introduce a time feedback mechanism to correct the grinding time of each batch of the products so as to lead the grinding thickness of each batch of the products to reach the target thickness value, thus the situation that electrical property and the yield of a chip are reduced as the difference value between the grinding thickness and the target thickness valve is overlarge is prevented, and the probability of the rejection rate is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, more specifically, to a chemical mechanical polishing method and system. Background technique [0002] With the rapid development of ultra large scale integration (ULSI, Ultra Large Scale Integration), the manufacturing process of integrated circuits has become more and more complex and refined, and the requirements for the flatness of the wafer surface have become more and more stringent. However, the widely used multi-layer wiring technology will cause the surface of the chip to be uneven, which is extremely unfavorable for graphics production. Therefore, it is necessary to planarize the chip so that each layer of wiring has a high global flatness. At present, CMP (Chemical Mechanical Polishing) is the best method to obtain high global flatness, especially after the semiconductor manufacturing process enters the sub-micron (sub-micron) field, CMP has become an indispensable ...

AI Technical Summary

Problems solved by technology

[0005] However, in actual production, it is found that the semiconductor chips manufactured by grinding the silicon oxide insulating layer for a fixed time often have reduced electrical properties and yield, and cannot meet the design requirements.

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