Peak value sampling retaining circuit and method thereof used for switch power supply

Abstract

The invention discloses a peak value sampling retaining circuit and a method thereof used for a switch power supply, wherein the peak value sampling retaining circuit comprises a peak value sampling circuit, a compensating circuit, a peak value retaining circuit, a peak value output buffering circuit and a clear circuit, the peak value sampling circuit is used for sampling peak value voltage at each time point of input signals, the compensating circuit is used for carrying out charging current compensation on sampling capacitance of the peak value sampling circuit, so as to enable the speed of the peak value sampling circuit to be quickened, the peak value retaining circuit is used for retaining voltage output by the peak value sampling circuit, the peak value output buffering circuit is used for enhancing load outputting capacity of the peak value retaining circuit, the clear circuit is used for timely clearing peak value voltage of a previous period, which is output by the peak value sampling circuit, so as to be convenient to carry out peak value sampling in a next period. In the invention, the peak value of input signals can better and faster reappear, and the peak value sampling retaining circuit can be applied on a switch power supply system.

Description

technical field [0001] The invention relates to a peak sampling and holding technology, in particular to a peak sampling and holding circuit used in a switching power supply and a method thereof. Background technique [0002] In a power supply system, the magnitude of the input voltage is an important factor that determines whether the system can work normally, so it is necessary to sample the line voltage through sample and hold. figure 1 It is the circuit diagram of the existing sample and hold circuit. The sample and hold circuit includes: a sampling circuit 110 and a hold circuit 111 . Described sampling circuit 110 comprises the control line 104 of sampling switch 102, sampling capacitor 105 and sampling switch, one end of sampling switch 102 is connected with input line 101, the other end of sampling switch 102 is connected with one end of sampling capacitor 105, the other end of sampling capacitor 105 grounding; when the control line 104 is at a high level, the samp...

AI Technical Summary

Problems solved by technology

[0005] The disadvantage of the existing sample-and-hold circuit is that when the hold switch 106 is turned on and the sample switch 102 is not turned on, the charge on the sampling capacitor will flow to the hold capacitor 108 to charge the hold capacitor until the charge on the sample capacitor 105 is The charging of the holding capacitor is completed only when the voltage is equal to the voltage on the holding capacitor 108, so that the final result is that the voltage on the holding capacitor 108 is the voltage when the sampling capacitor 105 and the holding capacitor 108 are balanced, rather than the voltage of the input line 101, The output voltage does not reproduce the voltage of the input signal very well

Since the existing technology does not have this link for compensating the charging current, the speed of the entire sample-and-hold circuit will decrease

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