Multi-micropacket parallel processing structure

Abstract

The invention discloses a multi-micropacket parallel processing structure, which aims to solve the problem that in a single-micropacket processing structure, the bandwidth of a physical layer and a link layer is not matched, so that the speed of the processing of the chip of a node controller to the communication among processors is reduced. The multi-micropacket parallel processing structure comprises an interface conversion module, a receiving module, a receiving buffer area, a message distribution module, a first protocol layer message FIFO (First In First Out), a second protocol layer message FIFO, a link state machine, a message assembly module, a send buffer area, a retransmission buffer area and a sending module, wherein the interface conversion module works under a physical layer clock domain, other modules work under a link layer clock domain, the interface conversion module comprises asynchronous receiving FIFO and asynchronous transmission FIFO, and data paths in the receiving module and the sending module are multi-path parallel data paths aiming at multi micropackets, and can process the multi micropackets in parallel. According to the invention, the bandwidth of the physical layer / the link layer is matched, so that the speed of the processing of the chip of the node controller to the communication among the processors is improved.

Description

technical field [0001] The invention relates to a flit processing structure in a processor interface access part in a node control chip. Background technique [0002] In the computer structure, the node control chip (Node Controller, NC), that is, the north bridge chip, is the core chip second only to the processor. [0003] Node control chip design techniques are developed in tandem with processor architecture and interface technology evolutions to match processor capabilities and requirements. Processor interface technology is gradually transitioning from front side bus FSB (Front Side Bus) to high-speed direct connection interface technology, such as AMD's HT (HyperTransport) interface and Intel's QPI (Quick Path Interconnect) interface. With the development of the processor direct connection interface technology, the multi-processor direct connection architecture has become the mainstream structure for building servers or mainframes. Note that the scale of multi-proces...

AI Technical Summary

Problems solved by technology

For example, according to the evaluation of ASIC chip manufacturer's process library and RAM IP (Intellectural Property, intellectual property core) library, under the 90nm process, standard units such as registers can work at about 1GHz, but the maximum operating frequency of IP such as RAM is 500MHz, and With the increase of RAM capacity, the working frequency shows a downward trend. Therefore, it is difficult for the single micro-packet processing structure to match the bandwidth of the physical layer and the link layer, resulting in an increase in data transmission delay and a reduction in the data transmission rate between direct-connected ports. , which in turn reduces the processing speed of the node controller chip for the communication between the processors

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