Method and system for reducing trace length and capacitance in a large memory footprint background

Abstract

A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Description

Background technique

[0001] Current printed circuit board (PCB) technology can arrange dual in-line memory module (DIMM) connectors using several different types of topologies. It is desirable to maximize the number of DIMM connectors per memory channel to achieve high memory capacity while operating at the highest possible frequency that the memory channel can support. One solution is to route all DIMM connectors close to the multicore sockets to keep trace lengths as short as possible. However, when more and more DIMM connectors are supported for higher storage capacity, the signal traces connecting the DIMM connectors are lengthened in conventional topologies. For example, in the case of double data rate 2 (DDR2) memory technology, 4 DIMM connectors per memory channel routed in conventional topologies can achieve marginal results at 667MHz.

[0002] Also, by using through-hole DIMM connectors and by placing the through-hole DIMM connectors on only one side of the PCB, the...

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