Navigating-SoC (System On Chip) simulating, verifying and debugging platform

Abstract

The invention discloses a navigating-SoC (System On Chip) simulating, verifying and debugging platform, which comprises a navigating-SoC verifying plate and a PC (Personal Computer) host-computer environment, wherein an RISC (Reduced Instruction Set Computer) processor and an FPGA (Field-Programmable Gate Array) are integrated onto the navigating-SoC verifying plate, and the PC host-computer environment is used for assisting the debugging and the analysis of a designer. A navigating IP (Internet Protocol) is realized on the FPGA, and the support for a hanging/operating mode is added. According to a hardware-hanging/operating state, a navigation-interrupting program is divided into a hardware-hanging period and a hardware-operating period, the introduction of intermediate-frequency data into the SoC verifying plate is finished through a UDP (User Datagram Protocol)/USB (Universal Serial Bus) protocol by a PC host computer at the hanging period, and debugging information is sequentially transmitted to the PC host computer by the SoC verifying plate. In the invention, the operating time of a code on the RISC processor is also accurately analyzed by utilizing a timer resource on the SoC verifying plate, and the real-time property of software and hardware can be analyzed. A PC host-computer end comprises a GUI (Graphical User Interface), a UDP/USB communication thread and a background database, so that a perfect verifying environment is provided for the designer.

Description

technical field [0001] The invention relates to the field of SoC (System On Chi, system on chip) verification and debugging, in particular to a device platform capable of emulating, verifying and debugging a navigation SoC chip. [0002] Background technique [0003] Global Navigation Satellite System (GNSS) has been widely used in various fields in the past few decades. At present, GNSS includes GPS of the United States, GLONASS of Russia, Compass (Beidou) of China and Galileo system of the European Union. In the civilian field, most mobile devices have navigation functions, which provide great convenience for people's travel. Many vehicles are equipped with GPS navigation equipment, which greatly simplifies the management of the transportation industry. In the military field, the navigation system is the top priority of modern warfare, and the core of these devices is the navigation chip. In the field of navigation chip design, there is a certain gap between domestic a...

AI Technical Summary

Problems solved by technology

The sampling rate of navigation intermediate frequency data ranges from 4MHz to 17MHz, and the navigation IP runs at 30MHz to 100MHz. The processor needs tens of millions of clock cycles to process 1s of data, and the navigation algorithm often needs one minute of data to calculate the result. If you want to simulate Some special scenarios require tens of minutes of data, and it will take a very long time to completely use HDL simulator to simulate

[0010] 4. The storage capacity of navigation intermediate frequency data is large. Taking the sampling rate of 5.714MHz with 2bit precision as an example, 1 minute of data requires 85.71MB of data; if you need to simulate the processes of capture, tracking and calculation in different scenarios, It often takes 5 minutes or even longer, and the data volume will reach more than 400 MB. Therefore, efficient data storage, import and playback mechanisms are also problems that must be solved by the debugging platform

When the software code given by these existing solutions is downloaded to the RISC processor later, there will be loopholes that are difficult to debug, which seriously affects the design progress

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