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A chip-scale packaging and chip technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve problems such as increased manufacturing time, difficult manufacturing processes, and increased costs.
Active Publication Date: 2014-08-13
SILICONWARE PRECISION IND CO LTD
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However, the manufacturing process through the encapsulant 13 is difficult, and the conductive material 100 needs to be filled when forming the conductive via 10, so that the manufacturing time is increased and the cost is increased.
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[0075] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0076] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "upper", "top" and "one" quoted...
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Abstract
The invention discloses a chip-size package and a manufacturing method thereof. The chip-size package comprises: an encapsulation compound having opposite first and second surfaces, a first encapsulation compound disposed in the encapsulation compound and exposed to the encapsulation compound. and the conductive bump on the second surface, the chip embedded in the encapsulant and exposed on the first surface of the encapsulant, the dielectric layer provided on the first surface of the encapsulant, the conductive bump and the chip, The circuit layer arranged on the dielectric layer, the conductive blind holes arranged in the dielectric layer to electrically connect the circuit layer, electrode pads and conductive bumps, and the barriers arranged on the dielectric layer and the circuit layer solder layer. Therefore, other electronic devices can be directly externally connected through the conductive bump to form a stack structure, which effectively simplifies the manufacturing process.
Description
technical field [0001] The present invention relates to a package and its manufacturing method, in particular to a chip size package and its manufacturing method. Background technique [0002] With the evolution of semiconductor technology, different packaging product types have been developed for semiconductor products. In order to pursue thinner, thinner and smaller semiconductor packages, a chip scale package (CSP) has been developed, which is characterized in that Chip-scale packages are only equal to or slightly larger than the chip size. [0003] U.S. Patent Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668, and 6,433,427 disclose a traditional CSP structure, which is to directly form a build-up layer on a chip without using chip carriers such as substrates or lead frames, and uses redistribution layers. , RDL) technology to reconfigure the electrode pads on the chip to the desired position. [0004] However, the disadvantage of the above-mentioned CSP structure is tha...
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