Universal package substrate, package structure and package method
A technology for packaging substrates and packaging structures, which is used in semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of long time period and high packaging cost, and achieves reduction of packaging cycle and packaging cost. Flexible connection methods Effect
Inactive Publication Date: 2012-05-09
TSINGHUA UNIV
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Problems solved by technology
[0004] The present invention aims at the defects of high packaging cost and long time period in existing small-batch integrated circuit products and their sample verification, and provides a general packaging substrate, packaging structure and packaging method that can overcome the above defects
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[0020] The general packaging substrate, packaging structure and packaging method according to the present invention will be described in detail below with reference to the accompanying drawings.
[0021] Such as figure 2 As shown, the general packaging substrate 10 according to the present invention includes a first substrate 102 and a silicon interposer 103, and a layer of the first substrate 102 and a lower surface of the silicon interposer 103 is formed The upper surface of the substrate 102 and the lower surface of the silicon insertion layer 103 are electrically connected to a plurality of bumps 106, and a plurality of bonding pads are formed on the upper surface of the silicon insertion layer 103. The wire bonding pads are respectively electrically connected to the plurality of bumps 106 through silicon vias 105 .
[0022] Wherein, the first substrate 102 can be an organic substrate, a silicon substrate or a ceramic substrate, and the design of parameters such as the s...
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Aiming at the defects that the existing small-batch integrated circuit product and sample validation thereof are high in packaging cost and long in time cycle, the invention provides a package substrate and a package structure which are used for overcoming the defects. The universal package substrate provided by the invention comprises a first substrate (102) and a silicon interposed layer (103), wherein multiple salient points (106) are formed between the upper surface of the first substrate (102) and the lower surface of the silicon interposed layer (103) and used for electrically connecting with the upper surface of the first substrate (102) with the lower surface of the silicon interposed layer (103) together; and the upper surface of the silicon interposed layer (103) is provided with multiple routing pads, and the multiple routing pads are respectively electrically connected with the multiple salient points (106) through silicon through holes (105).
Description
technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a general packaging substrate, packaging structure and packaging method. Background technique [0002] Ball Grid Array (BGA) packaging technology is an advanced high-performance area array packaging technology developed after the 1990s. Due to the advantages of short legs and good coplanarity, the application in light, small, and high-performance devices has grown rapidly, and has developed into a mature high-density packaging technology. in, figure 1 A schematic diagram of an existing flip-chip BGA package is shown. [0003] However, the current BGA package is at the stage where the chip design and package design are separated, which makes the substrate design different for different chips, that is, independently developed chips need to be equipped with a separately designed package substrate. Therefore, whether it is a sample or a product All require the research and d...
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IPC IPC(8): H01L23/492H01L23/00H01L21/60
CPCH01L2224/45124H01L23/147H01L23/49827H01L23/488H01L25/0655H01L23/3128H01L2924/15311H01L2224/48091H01L2224/85447H01L2224/45147H01L2224/32225H01L24/85H01L24/45H01L2924/157H01L2224/73204H01L24/48H01L2224/48465H01L2224/85424H01L2224/48227H01L2224/48471H01L2224/45144H01L2224/16225H01L2224/85444H01L2224/73265H01L24/73H01L23/49816H01L23/49833H01L24/29H01L24/32H01L24/92H01L2224/29339H01L2224/48624H01L2224/48644H01L2224/48647H01L2224/48724H01L2224/48744H01L2224/48747H01L2224/48824H01L2224/48844H01L2224/48847H01L2224/85181H01L2224/85186H01L2224/92247H01L2924/01047H01L2924/14H01L2924/15787H01L2924/181H01L2924/00014H01L2924/00015H01L2924/00012H01L2924/00H01L24/81H01L2924/01013H01L2924/01079
Inventor 蔡坚浦园园王谦郭函
Owner TSINGHUA UNIV