CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof

Abstract

The invention provides a CMOS (Complementary Metal Oxide Semiconductor) device and a manufacturing method thereof. The CMOS device comprises an NMOS (N-channel Metal Oxide Semiconductor) transistor and a PMOS (P-channel Metal Oxide Semiconductor) transistor, and stress side walls are formed at two sides of gates of the NMOS transistor and the PMOS transistor; and the stress side wall of the NMOS transistor is provided with tensile stress, and the stress side wall of the PMOS transistor is provided with compressive stress. When the CMOS device is manufactured, stress is remembered in a channel region of the NMOS transistor by using a stress memory technique, and meanwhile, the stress side walls are formed on the gates of the NMOS transistor and the PMOS transistor, thus, a favorable stress effect is provided, and the structure of the device is simplified.

Description

technical field [0001] The invention relates to the technical field of semiconductors, and more specifically, the invention relates to a CMOS device using strain memory technology and a manufacturing method thereof. Background technique [0002] In semiconductor devices, especially MOS devices, one of the main ways to increase the switching frequency of field effect transistors is to increase the driving current, and the main way to increase the driving current is to increase the carrier mobility. An existing technique for improving carrier mobility of field effect transistors is strain memory technology (StressMemorization Technique, referred to as SMT), which increases carrier mobility in the channel by forming stable stress in the channel region of the field effect transistor. Generally, tensile stress can make the molecular arrangement in the channel region more loose, thereby improving the mobility of electrons, which is suitable for NMOS transistors; while compressive ...

AI Technical Summary

Problems solved by technology

[0014] The existing manufacturing process of CMOS devices with strain memory effect has the following problems: although the stress of the strained layer can be memorized in the channel region of the bottom transistor by spike annealing, the stress is usually smaller than that produced in the channel region when the strained layer is retained. stress

However, if a thicker strain layer is retained, it will easily affect subsequent processes such as the manufacture of contact holes.

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