Input vector monitoring concurrency built-in self-test circuit based on comparator and response analyzer

Abstract

An input vector monitoring concurrency built-in self-test circuit based on a comparator and a response analyzer relates to a test device of a SOC. In the current test, hardware cost is high; test time delay is long so that several circuits which have many input pins can not be monitored. By using the circuit of the invention, the above problems can be solved. A detected integrated circuit has n original input signals. The t original input signals are selected from the original input signals to be address signals and the n-t original input signals are selected to be non-address signals. Combinations of the t address signals are different. The signal is selected through an alternative multiplexer and the signal is sent to a test generator and the detected integrated circuit. The comparator compares the selector signal with a column output signal and sends a comparison signal to the test generator. The test generator and the detected integrated circuit issue an output signal and an actual output signal to the response analyzer respectively. The response analyzer compares the two signals and sends a test result. The circuit can be used for detecting the circuit which can not be detected in the past.

Description

technical field [0001] The invention relates to a testing device for SOC. Background technique [0002] In the past forty years, the development of integrated circuits has followed Moore's Law, that is, the size of integrated circuits will double every eighteen months, and now it has entered the deep submicron stage. As the scale and integration of integrated circuits continue to increase, the manufacturing cost of the chip is also reduced. However, the increase in the complexity of the chip makes the testing cost of the chip more and more high. Since the chip test cost is a part of the total chip cost, which makes the chip test cost account for an increasing proportion of the total cost, so how to reduce the chip test cost has become a problem of great concern to people. [0003] The development of semiconductor technology has greatly improved the performance of VLSI, especially processors. However, as the size of transistors and interconnects decreases, supply voltages d...

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to solve the problems of high hardware cost and excessive test delay in the existing input vector monitoring concurrent built-in self-test, so that some circuits with more input pins cannot be monitored, and a new method is proposed. A Comparator Response Analyzer Based Input Vector Monitoring Concurrent Built-In Self-Test Circuit

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