Check patentability & draft patents in minutes with Patsnap Eureka AI!

Forming method for Cu interconnect line diffusion barrier of integrated circuit

A technology for integrated circuits and barrier layers, which is applied in the field of construction of Cu interconnection diffusion barrier layers in integrated circuits, and can solve the problems of reducing device performance, barrier layers cannot be deposited uniformly, and insulation layers cannot be completely covered.

Inactive Publication Date: 2012-06-13
NINGBO INST OF MATERIALS TECH & ENG CHINESE ACADEMY OF SCI
View PDF1 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the large trench aspect ratio and the deposited barrier layer is very thin, the barrier layer cannot be uniformly deposited on the sidewall and bottom wall of the trench, so that the barrier layer 3 cannot completely cover the insulating layer 1, and the Cu wire and the low The k insulating layer is in direct contact and interdiffusion occurs, which reduces the performance of the device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Forming method for Cu interconnect line diffusion barrier of integrated circuit
  • Forming method for Cu interconnect line diffusion barrier of integrated circuit
  • Forming method for Cu interconnect line diffusion barrier of integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

preparation example Construction

[0068] The present invention provides a more preferred preparation method, comprising steps:

[0069] (1) Low-k materials in integrated circuits (such as SiO 2 , SiOpCq, SiOpCqHr, SiOpFq, SiN or SiCN layer, wherein p is 0-2, q or r is 0-1) a Ta or TaN barrier layer with a thickness less than 10 nm is deposited on the sidewall and bottom of the channel;

[0070] (2) Deposit a Cu alloy seed layer with a thickness of 10nm to 250nm on the surface of the Ta or TaN barrier layer, wherein the alloy seed layer contains Cu and a doping element, and the doping element is Cr and Mn, Al, Ti, Mg , or at least one of Ni, the content of the doping element is 0.05at% to 20at%, based on the total number of atoms of the Cu alloy seed layer, thereby forming a diffusion barrier layer with an alloy seed layer deposited on the surface;

[0071] (3) annealing the diffusion barrier layer with the alloy seed layer deposited on the surface obtained in step (2) (such as at a temperature of 300-600° C. ...

Embodiment 1

[0098] Such as Figure 1a shown in SiO 2 In the insulating layer channel 2, a layer of Ta film 3 with a thickness of less than 10 nm is deposited by magnetron sputtering, covering the upper surface of the insulating layer and the side walls and bottom of the channel, and then a layer of Ta film 3 is deposited by magnetron sputtering A Cu alloy seed layer 4 with a thickness of 10nm to 250nm, such as Figure 1b shown. The contents of Mn and Cr in the Cu alloy range from 0.05 at% to 20 at%.

[0099] then to Figure 1b The device with the structure shown is subjected to heat treatment, the heat treatment temperature is 200°C-600°C, and the heat treatment time is 5min-3h. The heat treatment atmosphere can be vacuum or Ar protection atmosphere. Under this condition, the Mn and Cr elements in the Cu alloy will move to the positions where the first barrier layer cannot cover and cannot provide sufficient isolation respectively under the driving force of the interface reaction, and...

Embodiment 2

[0102] Such as Figure 2a shown in SiO 2 In the insulating layer channel 2, a layer of Ta film 3 with a thickness of less than 10 nm is deposited by magnetron sputtering, covering the upper surface of the insulating layer and the side walls and bottom of the channel, and then a layer of Ta film 3 is deposited by magnetron sputtering A Cu alloy seed layer 4 with a thickness of 10nm to 250nm, such as Figure 2b shown. The contents of Mn and Cr in the Cu alloy range from 0.05 at% to 20 at%.

[0103] Such as Figure 2cAs shown, the main conductive layer 6 of Cu is electrochemically deposited on Figure 2b and fill the entire trench. then to Figure 2c The device with the structure shown is subjected to heat treatment, the heat treatment temperature is 200°C-600°C, and the heat treatment time is 5min-3h. The heat treatment atmosphere can be vacuum or Ar protection atmosphere. Under this condition, the Mn and Cr elements in the Cu alloy will move to the positions where the fi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a forming method for a Cu interconnect line diffusion barrier of an integrated circuit. Specifically, the method comprises the following steps of: depositing a first diffusion barrier on the sidewall and bottom of a low-k material channel of the integrated circuit; and depositing a Cu alloy seed layer on the surface of the first diffusion barrier, performing annealing treatment, and forming a second diffusion barrier at a position which cannot be sufficiently isolated and covered by the Cu alloy seed layer and the first diffusion barrier. The diffusion barrier formed by the method is uniform in coverage and high in diffusion resistance.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a method for constructing a Cu interconnection diffusion barrier layer in an integrated circuit. Background technique [0002] In copper-based integrated circuits, a diffusion barrier layer is often laid between copper interconnects and low-k dielectric layers to prevent mutual diffusion between the two. At present, tantalum-based films (such as Ta, TaN, or Ta / TaN films) with a thickness of about 10 nanometers meet this requirement. [0003] However, with the continuous improvement of the integration level of semiconductor devices, the thickness of the barrier layer is required to be less than 10 nm, or a barrier layer with a considerable thickness can still form an effective coverage in a trench with a larger aspect ratio. At this level, conventional barrier layer formation methods have difficulty forming high-quality barrier layers with uniform coverage on the trench sidewal...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/768
Inventor 黄峰李金龙李洪波薛群基
Owner NINGBO INST OF MATERIALS TECH & ENG CHINESE ACADEMY OF SCI
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com