IP (Internet protocol) core verification system

A verification system and technology to be verified, applied in functional inspection, detection of faulty computer hardware, etc., can solve problems such as inability to debug SOC system software, prolong project development time, and inconvenient porting of test incentives, saving development time , easy to transplant, debug simple effect

Active Publication Date: 2012-06-20
HISENSE VISUAL TECH CO LTD
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

In contrast, the test stimulus written by it cannot be easily transplanted, so the SOC system software cannot be debugged in the hardware simulation

Method used

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  • IP (Internet protocol) core verification system
  • IP (Internet protocol) core verification system
  • IP (Internet protocol) core verification system

Examples

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Example

[0029] Such as figure 2 As shown, figure 2 The CPU model 222 in corresponds to figure 1 The processor model 102 in, which can run the test case 400, constitutes the joint simulation engine 302.

[0030] The processor model 102 (or the CPU model 222) is connected to the AHB system bus 300 through the AHB Master interface and transmits the bus signal to the IP core 104 to be verified through the AHB system bus 300. In this embodiment, figure 1 The IP core 104 to be verified shown in may be a USB host controller 204 (for example, a USB2.0 host controller), and the USB host controller 204 is connected to the AHB system through an AHB bridge 212 (a connector with a protocol conversion function) Bus 300.

[0031] In the above technical solution, preferably, the CPU model 222 is written in C-like language, and the test case 400 is written in C language.

[0032] In the above technical solution, preferably, the C-like language is System C language.

[0033] In the above technical solution,...

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Abstract

The invention provides an IP (Internet protocol) core verification system which comprises a processor model and an IP core to be verified, wherein the processor model is used for running the written test case and translating the operation executed by the test case into a bus signal after receiving an enable signal from a simulation tool, and transmitting the bus signal to the IP core to be verified; the IP core to be verified communicates with the processor model, receives the bus signal from the processor model and executes the operation corresponding to the bus signal; and the execution result of the IP core to be verified is compared with an expected result of the test case to confirm the verification result. According to the technical scheme of the invention, the occupation of the simulation resources can be reduced, the simulation time is reduced, the software/hardware interface integration time is shortened, and the development progress is accelerated.

Description

Technical field [0001] The present invention relates to the technical field of integrated circuits, in particular, to an IP core verification system for IP verification in integrated circuit design. Background technique [0002] USB (Universal Serial Bus) has become the mainstream industrial interface standard in the industry due to its advantages such as fast transmission speed, support for plug-and-play and hot-plugging, flexible power supply, simple bus structure, flexible use and expansion, etc. (System on Chip) has been widely used in design. In a typical application case, USB IP, as a sub-module in the SOC, has a complicated interconnection and communication relationship with other sub-modules, and is also controlled by the main CPU of the system. In such a complex system, how to verify the correctness of the USB IP design and the integrity of its work with other modules of the SOC system is very critical to the success of the project. [0003] The real working environment ...

Claims

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Application Information

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IPC IPC(8): G06F11/26
Inventor 李金亭
Owner HISENSE VISUAL TECH CO LTD
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