Cooperative simulation/verification method and device for software and hardware

A software-hardware collaboration and verification device technology, applied in instrumentation, computing, electrical digital data processing, etc., to reduce costs, accelerate development, and facilitate hardware verification

Inactive Publication Date: 2012-06-27
HISENSE HIVIEW TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The inventor found that the above two improvement methods both focus on the verification of the hardware, and the software running on the PC side is related to a specific project, and has certain differences from the software in the SoC, and cannot be used directly or with only a small amount of modification for the system SoC

Method used

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  • Cooperative simulation/verification method and device for software and hardware
  • Cooperative simulation/verification method and device for software and hardware
  • Cooperative simulation/verification method and device for software and hardware

Examples

Experimental program
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Effect test

Embodiment 1

[0055] Preferred Embodiment 1: The SoC design to be verified is mapped in the FPGA by means of burning. The PC is connected to the corresponding USB, serial port or PCI communication device on the FPGA through its USB, serial port, PCI and other communication devices. The FPGA communication device is connected to the bus master, and the bus master is connected to the SoC design. The PC successfully emulates the CPU in the SoC. SoC is designed as the realization of other hardware parts except CPU in FPGA, including on-chip bus (AXI, AHB, etc.), and various IPs with on-chip bus interface.

[0056] Use a C / C++ compiler in the PC environment (such as GNU GCC, etc.) to compile the SoC software into a binary file whose target machine is a PC, develop and run the USB IP driver software required by the SoC design. The PC sends a stimulus signal to the SoC design, and the SoC design responds to the stimulus signal and feeds a response signal back to the PC. Run the SoC software on th...

Embodiment 2

[0059] Preferred Embodiment 2: Take the application of the software-hardware co-simulation / verification device of the present invention in DDRII SDRAM IP (intellectual property core) verification as an example to illustrate the process of hardware verification.

[0060] Compile the SoC without CPU including DDRII SDRAM IP with the compilation tool QuartusII corresponding to FPGA and download it into FPGA, then this FPGA is equivalent to the actual chip of SoC.

[0061] Connect the FPGA to the software running terminal PC. The specific method of connection is: the communication device of FPGA and the communication device of software running terminal are connected to form a communication unit together to realize the information transmission between FPGA and software running terminal.

[0062] Use c / c++ to write driver software on the software running terminal. If you need to access the SoC registers in the FPGA, use the ReadAPI / WriteAPI provided by this device, and wait for the...

Embodiment 3

[0065] Preferred Embodiment Three: The process of hardware verification is illustrated by taking the application of the software-hardware co-simulation / verification device of the present invention in DDRII SDRAM IP (intellectual property core) verification as an example.

[0066] Compile the CPU-less SoC with DDRII SDRAM IP using the compiling tool ISE corresponding to the FPGA and download it into the FPGA, then this FPGA is equivalent to the actual chip of the SoC.

[0067] Connect the FPGA to the software running terminal PC. The specific method of connection is: the communication device of FPGA and the communication device of software running terminal are connected to form a communication unit together to realize the information transmission between FPGA and software running terminal.

[0068] Use c / c++ to write driver software on the software running terminal. If you need to access the SoC memory in the FPGA, use the ReadAPI / WriteAPI provided by this device, and wait for...

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Abstract

The invention discloses a cooperative simulation/verification method for software and hardware, which uses a software operating terminal to simulate CPU in SoC design to develop/operate the software and develops the software during hardware simulation/verification. The method comprises the steps of mapping the SoC design to a FPGA (Field Programmable Gata Array); connecting the SoC design to the software operating terminal through a bus main device and an FPGA communication device; developing the software required by the SoC design and operating the software at the software operating terminal to send an excitation signal to the SoC design; and responding to the excitation signal by the SoC design, wherein the responding signal is fed back to the software operating terminal. The invention discloses a cooperative simulation/verification device for software and hardware. The device comprises the FPGA mapped to the SoC design without the CPU and the software operating terminal having the software development function and/or operating function. The bus main device converts the read-write operation of the software to read-write operation of the bus.

Description

technical field [0001] The invention relates to a software and hardware co-simulation / verification method and device. Background technique [0002] As the integrated circuit process enters ultra-deep submicron, the integration level of a single chip is greatly increased, and IC design has entered the SoC design stage. A SoC system generally includes CPU, on-chip bus, memory, and various peripherals. The design of SoC includes not only the design of the hardware circuit, but also the design of the software running on the CPU on the chip. [0003] FPGA verification is to map the SoC design to be tested after the front-end simulation to the reconfigurable hardware platform based on the FPGA device in a certain way, establish a SoC design prototype, fully imitate the chip behavior, and run the test on it Programs that implement methods for verifying SoC designs. After the SoC passes the front-end simulation, the RTL-level code or the synthesized netlist is mapped to the FPGA,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 赵守磊
Owner HISENSE HIVIEW TECH CO LTD
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