Cooperative simulation/verification method and device for software and hardware

Abstract

The invention discloses a cooperative simulation / verification method for software and hardware, which uses a software operating terminal to simulate CPU in SoC design to develop / operate the software and develops the software during hardware simulation / verification. The method comprises the steps of mapping the SoC design to a FPGA (Field Programmable Gata Array); connecting the SoC design to the software operating terminal through a bus main device and an FPGA communication device; developing the software required by the SoC design and operating the software at the software operating terminal to send an excitation signal to the SoC design; and responding to the excitation signal by the SoC design, wherein the responding signal is fed back to the software operating terminal. The invention discloses a cooperative simulation / verification device for software and hardware. The device comprises the FPGA mapped to the SoC design without the CPU and the software operating terminal having the software development function and / or operating function. The bus main device converts the read-write operation of the software to read-write operation of the bus.

Description

technical field [0001] The invention relates to a software and hardware co-simulation / verification method and device. Background technique [0002] As the integrated circuit process enters ultra-deep submicron, the integration level of a single chip is greatly increased, and IC design has entered the SoC design stage. A SoC system generally includes CPU, on-chip bus, memory, and various peripherals. The design of SoC includes not only the design of the hardware circuit, but also the design of the software running on the CPU on the chip. [0003] FPGA verification is to map the SoC design to be tested after the front-end simulation to the reconfigurable hardware platform based on the FPGA device in a certain way, establish a SoC design prototype, fully imitate the chip behavior, and run the test on it Programs that implement methods for verifying SoC designs. After the SoC passes the front-end simulation, the RTL-level code or the synthesized netlist is mapped to the FPGA,...

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Problems solved by technology

[0007] The inventor found that the above two improvement methods both focus on the verification of the hardware, and the software running on the PC side is related to a specific project, and has certain differences from the software in the SoC, and cannot be used directly or with only a small amount of modification for the system SoC

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