Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method

Abstract

The invention discloses a multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method, which relate to field programmable gate array technology, are used for realizing debug and observation of an internal signal of an FPGA, and mainly comprise a multiplex JTAG interface, an on-chip logic analyzer circuit and a human-computer interface module, wherein the on-chip logic analyzer circuit can be used for selecting different sampling signals on line; and the human-computer interface module is used for receiving sampling signals and triggering states simultaneously. The multiplex JTAG interface-based FPGA on-chip logic analyzer system and method have the beneficial effects that: a method for utilizing the multiplex JTAG interface to realize the on-chip logic analyzer system is provided, and the sampling signals are selected on line, so that the requirement of the on-chip logic analyzer system for on-chip sampling storage resources is reduced, wherein the required storage resource quantity is inversely proportional to the number of sampling signal groups; and a method capable of realizing time division transmission of the sampling signals and triggering state information of JTAG is provided, so that the efficiency for debugging the FPGA is improved.

Description

technical field [0001] The present invention relates to Field Programmable Gate Array (FPGA) technical field, relate in particular to embedded debug system multiplexing Field Programmable Gate Array (FPGA) Internal Joint Test Action Group (JTAG) interface and online setting register, to realize the field programmable A method for observing internal signals of a gate array (FPGA). Background technique [0002] In the process of verifying an IC design using hardware logic such as a field programmable gate array (FPGA), a logic analyzer is usually required to observe the internal signals of the hardware logic. A verification method is similar to the SignalTap tool launched by Altera, which generates configuration files through logic synthesis and wiring together with these function codes and tested codes, and downloads them to hardware logic such as Field Programmable Gate Array (FPGA), and then during the test process The signal is sampled and transmitted to the host computer...

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Problems solved by technology

[0013] The object of the present invention is to provide a kind of logic analyzer system and method in the FPGA chip of multiplexing JTAG interface, this system is through multiplexing Field Programmable Gate Array (FPGA) internal Joint Test Action Group (JTAG) interface and online setting sampling The method of selecting registers is used to overcome the shortcomings of using too many on-chip memory resources and complex communication interfaces in the prior art, and at the same time, a method of time-sharing transmission of sampling data and trigger status information using the Joint Test Action Group (JTAG) interface is proposed protocol to improve the debugging efficiency and reliability of the field programmable gate array (FPGA) on-chip logic analyzer

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