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Test circuit and test method for testing before chip packaging

A technology for testing circuits and chip packaging, applied to circuits, measuring electricity, measuring electrical variables, etc., can solve problems such as low sensitivity

Active Publication Date: 2015-07-29
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of this, the main purpose of the present invention is to aim at the technical problem of low sensitivity of the test circuit used to test whether the circuit in the chip and the dielectric layer are damaged during the molding process of the adhesive pad in the prior art, and to provide a More refined, suitable for continuous improvement of integrated circuit processing technology, test circuit and test method for testing before chip packaging

Method used

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  • Test circuit and test method for testing before chip packaging
  • Test circuit and test method for testing before chip packaging
  • Test circuit and test method for testing before chip packaging

Examples

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Effect test

Embodiment 1

[0029] Figure 4 and Figure 5 A specific implementation manner of a test circuit for testing before chip packaging of the present invention is shown. A test circuit used for testing before chip packaging includes multiple layers of metal located at different depths in the chip. Specifically, the test circuit is arranged in the chip below the bonding pad 203 for the epitaxial gold wire 201, which includes a first layer of metal 204, a second layer of metal below the first layer of metal 204, and A third layer of metal 202 located below the second layer of metal. Wherein, the horizontal widths of the first layer of metal 204, the second layer of metal and the third layer of metal 202 are similar to the adhesive pad 203, so these three layers of metal can positively attach the adhesive pad 203 The damage to the circuitry in the underlying chip is fully manifested.

[0030] like Figure 4 As shown, the second metal layer includes a plurality of ring structures, such as Fig...

Embodiment 2

[0034] Image 6 and Figure 7 A specific implementation manner of a test circuit for testing before chip packaging of the present invention is shown. A test circuit for testing before chip packaging, which is arranged in the chip below the bonding pad 303 of the wire 301 made of epitaxial gold wire or aluminum wire material, including the first layer of metal 304, located in the first A second layer of metal below the layer metal 304, and a third layer of metal 302 below the second layer of metal. Wherein, the horizontal widths of the first layer of metal 304 , the second layer of metal and the third layer of metal 302 are similar to those of the adhesive pad 303 . like Image 6 As shown, the second metal layer includes a plurality of ring structures, such as Figure 7As shown, each ring structure includes an inner metal 308 and an outer metal 307 located in the same metal layer, and a dielectric layer 305 is between the inner metal 308 and the outer metal 307 . Each inne...

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Abstract

The invention provides a test circuit for testing a chip before package, which is arranged in a chip arranged under an adhesion pad for lead epitaxy comprises first-layer metal and second-layer metal located under the first-layer metal. The second-layer metal comprises a plurality of annular structures, and each annular structure comprises inner-layer metal and outer-layer metal. Each inner-layer metal is connected with the outer-layer metal through one piece of first conducting metal, and the cross sectional area of each piece of first conducting metal is smaller than that of the inner-layer metal. The test circuit is suitable for electrical property testing performed before the package in continuously-improved integrated circuit technology.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a test circuit and a test method for testing before chip packaging. Background technique [0002] like figure 1 and figure 2 As shown, the encapsulation of the die is to press one end of the wire 102 of the gold wire or aluminum wire on the bonding pad 106 (Bond pad) around the chip 101 with a mechanical steel nozzle, and press the other end on the lead frame. on the metal pin 103. In the "basement" of the chip, the electrical signal can be sent to the uppermost adhesive pad 106 after the calculation is completed through CMOS, and then connected to the metal pin 103 of the package shell through the wire 102. In addition, it can also be connected with the flip-chip package. outside connection. Then, glue sealing is carried out, that is, the chip 101 and pins after wiring are placed in the mold 105, epoxy resin 104 (Epoxy) is injected, and then baked and hardened t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544G01R31/00G01R31/02
CPCH01L2224/48091H01L2224/48247H01L2924/181
Inventor 甘正浩
Owner SEMICON MFG INT (SHANGHAI) CORP