Double-light-resistance wall and preparation method thereof

Abstract

The invention discloses a double-light-resistance wall and a preparation method of the double-light-resistance wall applied for through-silicon vias wafer level package. The preparation method mainly comprises the steps of glass cleaning, photoresist coating, exposure, development, baking and the like. In the exposure step, a double-light-resistance wall light cover is adopted, and the exposure energy is 800 to 1000mJ / cm<2>; and in the development step, 10 to 11g / L of Na2CO3 solution is adopted, and the development lasts 3 to 5 minutes. The double-light-resistance wall obtained by the method comprises a plurality of double-light-resistance wall units, wherein each double-light-resistance wall unit comprises an inner light resistance wall, an outer light resistance wall and a cutting passage, the outer light resistance wall is arranged on the periphery of the inner light resistance wall, and the cutting passage is arranged between the inner resistance wall and the outer resistance wall. The double-light-resistance wall has the advantages that the gluing area between the wall and wafers can be effectively increased, and in addition, the air bubble no-glue risk caused by glue overflowing and nonuniform glue can be reduced.

Description

technical field [0001] The invention relates to a double photoresist wall, in particular to a double photoresist wall for larger-sized chips used in through-silicon hole wafer level packaging and a preparation method thereof. Background technique [0002] In the field of Through Silicon Via (TSV) wafer packaging, design and prepare photoresist walls on the surface of optical glass, and prepare photoresist walls with size requirements on the glass surface through steps such as coating photoresist, exposure, development, and baking. The photoresist wall (Cavity Wall) forms a lattice groove, similar to a cavity. At present, the design and preparation of the photoresist wall are all single-layer, which leads to insufficient bonding force between the photoresist wall (Cavity Wall) and the wafer (Wafer) when packaging larger-sized chips, so that in the subsequent During the manufacturing process, it is easy to cause packaging abnormalities such as delamination and Via hole leakag...

AI Technical Summary

Problems solved by technology

At present, the design and preparation of the photoresist wall are all single-layer, which leads to insufficient bonding force between the photoresist wall (Cavity Wall) and the wafer (Wafer) when packaging larger-sized chips, so that in the subsequent During the manufacturing process, it is easy to cause packaging abnormalities such as delamination and Via hole leakage; if only increasing the width of the photoresist wall will cause defects such as glue overflow and glue bubbles

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