Interrupt control method for Feiteng server

Abstract

The invention discloses an interrupt control method for a Feiteng server. The method comprises the following steps: initialization is performed; a hardware interrupt source generates corresponding types of interrupt signals through a hardware control logic component of a south bridge CS5536, outputs a public interrupt trigger signal through a router of an interrupt controller 8259A of the south bridge CS5536 and modifies corresponding interrupt bits in an internal register of the interrupt controller 8259A, and the public interrupt trigger signal is mapped by a bridge chip to be converted into interrupt messages and transmitted to a PCIE bus; and a Feiteng processor acquires the interrupt messages from the PCIE bus, enters an interrupt state, invokes a public interrupt receptance function and reads the internal register of the interrupt controller 8259A to acquire the interrupt bits so as to determine the hardware interrupt source and treat interrupts. The method provided by the invention can enable the Feiteng processor to receive interrupt messages of equipment CS5536 in a real-time manner and to respond and treat various interrupts accurately and in a real-time manner.

Description

technical field [0001] The invention relates to the technical field of operating system interruption, in particular to an interruption control method for a Feiteng server. Background technique [0002] The Phytium server adopts two Phytium processors, each processor is composed of 8 cores and 64 hard threads, and the processor frequency is 800MHz~1GHz. It provides 6 PCIE2.0 bus slots through point-to-point high-speed switching chips, and the highest single The IO frequency can reach 5Gbps. [0003] Feiteng server adopts PCI bus standard Southbridge CS5536, which integrates hardware interface control logic such as USB controller, IDE disk controller, audio controller, RTC real-time clock and keyboard and mouse PS / 2 interface controller. The monolithic 8259A includes 8 interrupt input pins, 1 interrupt output pin, 1 interrupt acknowledge pin, cascade pin and other control pins. Through cascading pins, multiple 8259As can be connected in series in a "master-slave" configurati...

AI Technical Summary

Problems solved by technology

There are two typical 8259A application methods: one is to use an independent 8259A chip to control the interrupt, and the peripheral device interrupt is directly input to the 8259A, and then passed to the processor through the interrupt output pin of the 8259A for interrupt processing; the other is to integrate In the application of 8259A in South Bridge CS5536, the device interrupt supported by CS5536 chip is directly processed through this interrupt controller. This integrated design method is generally only used on X86 series processor platforms, and has X86 architecture dependence.

Images