Signal receiving circuit, memory controller, processor, computer, and phase control method
A memory controller and signal receiving technology, which is applied in the field of signal receiving circuit, memory controller, processor, computer and phase control, can solve problems such as data transmission obstruction, reduce circuit scale, improve reliability, and eliminate phase Effect of change
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no. 1 Embodiment approach 〕
[0052] In the first embodiment, the phase difference between the reception signal and the clock signal is detected by the phase detection unit. A delay amount in units of a predetermined phase difference (reference phase difference) is set in the delay control unit based on the phase difference. In view of this, the delay control unit changes the phase of the received signal in units of the delay amount when the phase of the received signal is delayed within a range not exceeding the delay amount and the phase difference exceeds the predetermined phase difference. The predetermined phase difference is, for example, a phase difference in units of 90 degrees, and the delay amount is a delay amount in units of the phase difference. The range not exceeding the delay amount is a phase delay of less than 90 degrees if the delay amount is set to 90 degrees, for example.
[0053] refer to figure 1 This first embodiment will be described. figure 1 is a diagram showing an example of ...
no. 2 Embodiment approach 〕
[0074] In the second embodiment, multi-phase CLK signals are generated in units of predetermined phase differences, and delay amounts are set for DQ signals based on the CLK signals. A data holding unit for holding the DQ signal with the phase delay optimized is provided.
[0075] refer to image 3 This second embodiment will be described. image 3 It is a diagram showing an example of a signal receiving circuit, a memory controller, and a memory. exist image 3 in, right with figure 1 The same parts are given the same reference numerals.
[0076] The signal receiving circuit 2 is an example of the signal receiving circuit disclosed in the present application, and is a unit that receives, for example, a data signal from the memory 4 as a signal source. The memory 4 is constituted by, for example, a DIMM which is a DDR3 memory. The memory 4 includes an input buffer 20 and output buffers 22 and 24 corresponding to the signal receiving circuit 2 of the memory controller 6 ....
no. 3 Embodiment approach 〕
[0154] The third embodiment uses first delay information (dqphase1) and second delay information (dqphase2) as delay information (DQPHASE) obtained from a phase difference. In this case, the first delay information is a delay amount in units of a predetermined phase difference, and is a delay amount in which the phase of the phase reference signal is changed, for example, in units of 90 degrees. In addition, the second delay information is a delay amount for delaying the phase of the phase reference signal within a range not exceeding the delay amount in units of a predetermined phase difference.
[0155] refer to Figure 20 This third embodiment will be described. Figure 20 It is a diagram showing an example of a signal receiving circuit according to the third embodiment. exist Figure 20 in, right with image 3 The same parts are given the same reference numerals.
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