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Virtual memory system, virtual memory controlling method, and program

A technology of virtual storage and storage, which is applied to storage systems, instruments, and memory architecture access/allocation, etc. It can solve problems such as system performance deterioration and achieve the effect of avoiding write restrictions

Inactive Publication Date: 2012-10-03
SONY SEMICON SOLUTIONS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The swap-out and swap-in processes, as they occur, involve accessing storage devices and the occurrence of data transfers between storage and storage devices, thus temporarily degrading system performance from an application point of view

Method used

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  • Virtual memory system, virtual memory controlling method, and program
  • Virtual memory system, virtual memory controlling method, and program
  • Virtual memory system, virtual memory controlling method, and program

Examples

Experimental program
Comparison scheme
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no. 1 example

[0052] figure 1 is a schematic diagram showing the configuration of a virtual memory system to which a nonvolatile random access memory (NVRAM) according to the first embodiment of the present disclosure is applied.

[0053] The present virtual memory system 10 includes a CPU 20 as a virtual memory control section, a memory controller 30 , a nonvolatile random access memory (NVRAM) 40 and a system bus 50 .

[0054] The nonvolatile random access memory 40 is randomly accessible, and has an upper limit to the number of times of rewriting. Under the control of the CPU 20, the physical address space of the nonvolatile RAM 40 is accessed through the virtual address space.

[0055] The CPU 20 includes a processor unit 21 , a memory management unit (MMU) 22 and a cache memory 23 .

[0056] The CPU 20 also includes a translation look-aside buffer (TLB) 24 and a bus interface unit 25 .

[0057] The virtual memory system 10 according to the present embodiment is formed as a virtual m...

no. 2 example

[0191] Figure 14 is a schematic diagram showing the configuration of a virtual memory system to which a nonvolatile random access memory (NVRAM) according to a second embodiment of the present disclosure is applied.

[0192] The virtual memory system 10A according to the second embodiment of the present disclosure is different from the virtual memory system 10 according to the first embodiment in the following respects.

[0193] In the virtual memory system 10A, in addition to the nonvolatile random access memory 40, a volatile random access memory 40A such as DRAM is also connected to the memory controller 30A.

[0194] as above reference Figure 9 as well as Figure 10A with Figure 10B As described, in this embodiment, an NVM bit is added to each entry of the page directory table PDT11 and the page table PT11.

[0195] The virtual memory systems 10 and 10A according to the first and second embodiments of the present disclosure are compatible with both the nonvolatile r...

no. 3 example

[0214] Figure 18 is a schematic diagram showing the configuration of a virtual memory system to which a nonvolatile random access memory (NVRAM) according to a third embodiment of the present disclosure is applied.

[0215] The virtual memory system 10B according to the third embodiment of the present disclosure is different from the virtual memory system 10 according to the first embodiment in that the ECC circuit 26 is provided in the CPU 20A as a virtual memory control section.

[0216] Data read from the nonvolatile random access memory 40 is transferred to the cache memory 23 . In the case of data having ECC added thereto, the data after error detection and error correction by the ECC circuit 26 is transferred to the cache memory 23 .

[0217] Also, at the time of writing, the data in the cache memory 23 is transferred to the nonvolatile random access memory 40 through the memory controller 30 . This data is written with an ECC code attached thereto.

[0218] Incident...

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Abstract

Disclosed herein is a virtual memory system including a nonvolatile memory allowing random access, having an upper limit to a number of times of rewriting, and including a physical address space accessed via a virtual address; and a virtual memory control section configured to manage the physical address space of the nonvolatile memory in page units, map the physical address space and a virtual address space, and convert an accessed virtual address into a physical address; wherein the virtual memory control section is configured to expand a physical memory capacity allocated to a virtual page in which rewriting occurs.

Description

technical field [0001] The present disclosure relates to a virtual memory system, a virtual memory control method, and a program that are compatible with nonvolatile nonvolatile random access memory, have an upper limit on the number of times of rewriting, and allow random access. Background technique [0002] A current virtual memory system is composed of a memory management unit called MMU (Memory Management Unit) and virtual memory control software implemented as a function of an operating system. [0003] A virtual memory system having such a configuration is used in various systems as a system intended to use the physical memory space of a DRAM as a volatile memory. [0004] The virtual memory system divides and manages a physical memory (physical address) space in units of pages. The application that needs memory requests and guarantees the necessary virtual pages from the virtual memory system in advance before using the virtual pages. This is called demand paging. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F12/02
CPCG06F12/08G06F12/1009G06F2212/202
Inventor 中西健一
Owner SONY SEMICON SOLUTIONS CORP
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