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Semiconductor device manufacturing method utilizing stress memorization technology

A device manufacturing method and stress memory technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of cumbersome manufacturing methods and processes, and achieve the effect of improving performance and simplifying process steps

Active Publication Date: 2014-06-04
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The invention provides a semiconductor device manufacturing method using stress memory technology to solve the problem of tedious process in the existing manufacturing method

Method used

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  • Semiconductor device manufacturing method utilizing stress memorization technology
  • Semiconductor device manufacturing method utilizing stress memorization technology
  • Semiconductor device manufacturing method utilizing stress memorization technology

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Embodiment Construction

[0019] The semiconductor device manufacturing method using the stress memory technology provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form, and are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

[0020] Combine below Figure 1 to Figure 10 Describe in detail the semiconductor device manufacturing method using stress memory technology of the present invention, the manufacturing method includes the following steps:

[0021] Step S01: providing a substrate, a gate structure is formed on the substrate, and an active / drain region is formed in the substrate;

[0022] refer to figure 2 As shown, the material of the substrate 100 can be s...

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Abstract

The invention discloses a semiconductor device manufacturing method utilizing a stress memorization technology, which comprises the following steps: partially removing a formed stress layer; selectively etching area of the stress layer, which is required to form a metal silicide area; forming a side wall on the side wall of a grid electrode structure on the formed metal silicide area, so as to directly serve as a self-aligned metal silicide barrier layer; forming a metal silicide layer on the exposed source / drain area and the grid electrode structure, so as to simplify the process steps; and removing the side wall after the metal silicide layer is formed, and adopting a stress proximity effect technology to allow a CESL stress layer to be closer to a channel so as to improve the performance of the device.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a semiconductor device manufacturing method using stress memory technology (SMT). Background technique [0002] With the development of CMOS semiconductor device technology and proportional size reduction, stress engineering plays an increasingly important role in semiconductor technology and device performance; the introduction of stress in CMOS devices is mainly to improve the carrier mobility of the device. Tensile stress in the channel direction (longitudinal) of CMOS devices is beneficial to NMOS electron mobility, while compressive stress is beneficial to PMOS hole mobility, and tensile stress in the channel width direction (transverse) is beneficial to the carriers of NMOS and PMOS devices. The mobility is beneficial, and the compressive stress in the vertical channel plane direction (out-of-plane) is beneficial to the electron mobility of the NMOS device, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 郑春生
Owner SHANGHAI HUALI MICROELECTRONICS CORP