Dual-feedback power supply clamp used for on-chip electrostatic discharge protection

Abstract

The invention discloses a dual-feedback power supply clamp used for on-chip electrostatic discharge protection. The dual-feedback power supply clamp used for on-chip electrostatic discharge protection comprises an RC-triggered transistor feedback circuit between a VDD and a GND, wherein the feedback circuit comprises a P-type cascade transistor and an N-type cascade transistor and further comprises a resistor which is used for reducing the voltage of a big transistor when the circuit works normally; the feedback circuit is further provided with a filter potential point, an INV1OUT potential point, an INV2OUT potential point and a grid potential point. By using the dual-feedback power supply clamp provided by the invention, the P-type cascade transistor and the N-type cascade transistor are used to form the feedback circuit to effectively prolong the conduction time of the big transistor (Big FET(field effect transistor)) for electrostatic discharge (ESD) and current discharge, guarantee the complete release of electrostatic discharge pulses, inhibit the mistaken triggering of an electrostatic release protection circuit, and reduce the occupied area and electricity leakage of a power clamp circuit.

Description

technical field [0001] The invention relates to the design field of a chip electrostatic protection circuit in an integrated circuit I / O, in particular to a double-feedback power supply clamp for on-chip electrostatic discharge protection. Background technique [0002] In order to provide on-chip protection for the chip, power supply clamping protection between VDD and GND is required, usually by means of RC trigger (RC-trigger) a large-size transistor. On the one hand, in order to ensure that large-scale transistors remain fully on when an electrostatic discharge (ESD) pulse occurs, a large RC time constant (greater than or equal to the HBM pulse width, 1us) is required, which requires a large area of ​​capacitance, which not only causes Chip area is wasted, and for advanced technology, due to large leakage, it will cause large power consumption. On the other hand, a large RC time constant can cause false triggering of electrostatic discharge (ESD) protection devices when ...

AI Technical Summary

Problems solved by technology

[0003] The object of the present invention is to provide a kind of power supply clamp with double feedback for on-chip electrostatic discharge protection, to solve the problem that existing large capacitance design is used to increase RC constant, which will waste chip area and cause large power consumption, and single feedback design It is not easy to adequately guarantee the full effectiveness of electrostatic discharge (ESD) pulses

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