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Semiconductor packaging structure for stacking and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc.

Active Publication Date: 2012-10-17
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the present invention provides a stacked semiconductor package structure and its manufacturing method to solve the problems of warpage and heat dissipation in the existing stacked package (POP) technology

Method used

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  • Semiconductor packaging structure for stacking and manufacturing method thereof
  • Semiconductor packaging structure for stacking and manufacturing method thereof
  • Semiconductor packaging structure for stacking and manufacturing method thereof

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Embodiment Construction

[0018] The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. Furthermore, the directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside" or "side", etc., It is only for orientation with reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

[0019] Please refer to figure 1 As shown, the semiconductor package structure for stacking according to the first embodiment of the present invention is mainly applied to the lower package 100 as a stacked package (POP), and is used to combine an upper package 200. Hereinafter, the The stacked semiconductor package structure is directly referred to as the lower package 100 . In this embodiment, the lower package body 100 includes: ...

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Abstract

The invention discloses a semiconductor packaging structure for stacking and a manufacturing method thereof. The semiconductor packaging structure comprises a bottom substrate, a chip, an annular switchover substrate and packaging colloid. The bottom substrate is provided with a plurality of welding pads and a chip bearing area; the chip is fixedly arranged on the chip bearing area of the bottom substrate; a plurality of switchover assemblies and an opening are arranged on the annular switchover substrate; the switchover assemblies surround the opening and are electrically connected with the welding pads of the bottom substrate; the packaging colloid is filled in a gap between the bottom substrate and the annular switchover substrate, and is filled in the opening of the annular switchover substrate; and the packaging colloid in the opening is exposed to one top surface of the chip. With the adoption of the annular switchover substrate, the upper side and the lower side of a packaged body are slightly different in coefficient of thermal expansion, so that the warping rate is relatively lowered.

Description

technical field [0001] The present invention relates to a semiconductor package structure for stacking and a manufacturing method thereof, in particular to a semiconductor package structure for stacking and a manufacturing method thereof which utilizes a ring-shaped transfer substrate to reduce warpage defects. Background technique [0002] Nowadays, in order to meet the demands of various high-density packaging, the semiconductor packaging industry gradually develops various types of packaging designs, among which various system in package (SIP) design concepts are often used to structure high-density packaging products. Generally speaking, the system package can be divided into multi chip module (multi chip module, MCM), stacked package (POP), and package in package (package in package, PIP). The multi-chip module (MCM) refers to arranging several chips on the same substrate. After the chips are installed, all the chips are embedded with the same encapsulation gel, and can...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/367H01L21/56
CPCH01L2924/18161H01L2224/73265H01L2224/16225H01L2224/73204H01L2224/32145H01L2224/48227H01L2224/32225H01L2224/73253H01L2225/06562H01L2224/48145H01L24/73H01L2924/3511H01L2224/32245H01L2225/1041H01L2225/1058H01L2225/1094H01L2225/0651H01L2225/06506H01L2924/00012H01L2924/00
Inventor 沈明宗鄚智仁张惠珊
Owner ADVANCED SEMICON ENG INC
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