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Dual-loop low dropout regulator

A technology of low-dropout linear and linear voltage regulators, which is applied in the direction of instruments, electric variable adjustment, control/regulation systems, etc., can solve problems such as ESR fluctuations, increased chip area, large output current, etc., to reduce chip area and power Consumption, to ensure the effect of system stability

Inactive Publication Date: 2014-03-05
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In terms of LDO reliability, due to factors such as power-on establishment, limited power supply capacity, and LDO overload, the LDO is often in an unstable working state. Based on the above reasons, many problems will occur: (1) During the establishment of the LDO, the loop load The feedback mechanism prompts the power tube to output a large current, and the LDO power supply module may be pulled down, causing other modules in the system to fail; (2) When the LDO output is short-circuited or overloaded, the output current is too large, causing the temperature of the LDO to rise until it burns out
There are three traditional over-current protection designs, one is to use a comparator to detect whether the output of the power tube is over-current, and directly shut off the power tube after the over-current. The disadvantage of this circuit is that it takes a long time for the circuit to recover from the over-current. time; the second is the foldback current limit, which limits the output current after overcurrent to a small value, which will neither consume a lot of power nor take a long time to switch the circuit from overcurrent to It works normally, but its disadvantage is that the current limit value of the foldback current limit is within the normal working output current range of the LDO. When the fault is eliminated, the current limit loop is not easy to exit, resulting in the LDO not working normally, and the foldback current limit usually has an additional current limit. The loop and large adjustment tube increase the chip area; the third is a constant current limiting circuit, which limits the output current to a set overcurrent point when an overcurrent condition occurs. The traditional method is to use an independent The constant current loop of the constant voltage loop is used to monitor the output current of the power tube. When the overcurrent condition is met, the power tube is controlled to make the output current a set constant current value, such as smooth peak current limit technology, but logic is often used The control method is switched between the independent constant voltage loop and constant current loop, the control is complex and the additional adjustment tube in the constant current loop increases the chip area
[0005] In terms of LDO stability design, the LDO using off-chip capacitor compensation utilizes the traditional method of using the equivalent series resistance (Equivalent Series Resistance, ESR) of the external load capacitor to generate an effective zero point to achieve compensation, increasing the peak of the output transient response, and the ESR will Fluctuation, large dispersion, and the required ESR is large, it is difficult to achieve

Method used

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Embodiment Construction

[0021] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0022] Such as figure 1 As shown, the dual-loop LDO circuit of the present invention specifically includes: a first loop and a second loop. The first loop is a three-stage amplifier composed of the first amplification stage AMP1, the second amplification stage AMP2, the third amplification stage AMP3, the first compensation network CPNET1 and the second compensation network CPNET2, wherein AMP1, AMP2 and CPNET1 form an error Amplifier ERROR_AMP. The second loop is a three-stage amplifier composed of the second amplification stage AMP2, the fourth amplification stage AMP4, the fifth amplification stage AMP5 and the third compensation network CPNET3.

[0023] The specific connection relationship is: the positive input terminal of the first amplification stage AMP1 is connected to the external reference voltage source VREF as the input terminal ...

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Abstract

The invention discloses a dual-loop low dropout regulator, which comprises a first loop and a second loop, wherein the first loop is a three-level amplifier formed by a first amplifier stage, a second amplifier stage, a third amplifier stage, a first compensation network and a second compensation network, and a second loop is a three-level amplifier formed by a second amplifier stage, a fourth amplifier stage, a fifth amplifier stage and a third compensation network. According to the invention, a constant-voltage output of the LDO (Low Dropout Regulator) is controlled by the first loop, an output current of LDO is limited by the second loop so as to prevent the output current from exceeding an over-current point when an over-current condition appears, and the second compensation network and the output port of the LDO are externally connected with a load capacitor, so that a pseudo ESR (Equivalent Series Resistance) zero setting compensation network is integrated in the first loop, and the frequency compensation of the first loop is realized; and meanwhile, the second amplifier stage of the second loop and the second amplifier stage of the first loop are shared, so that the conventional dual-loop LDO circuit is simplified, and the area and the consumption of a chip are reduced.

Description

technical field [0001] The invention belongs to the technical field of power supply management, and in particular relates to the design of a low dropout linear regulator (LDO, Low Dropout Regulator). Background technique [0002] With the development of integrated circuits towards SoC (System on Chip), the power management unit is gradually integrated into the chip and plays an important role. As an important type in power management modules, LDOs are widely used because they can provide low-noise, high-precision stable power supply voltages for noise-sensitive analog modules. [0003] In terms of LDO reliability, due to factors such as power-on establishment, limited power supply capacity, and LDO overload, the LDO is often in an unstable working state. Based on the above reasons, many problems will occur: (1) During the establishment of the LDO, the loop load The feedback mechanism prompts the power tube to output a large current, which may cause the LDO power supply modu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05F1/56
Inventor 周泽坤吴传奎王霞谢海武石跃王卓明鑫张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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