A synchrophasor calculation method based on fpga hardware dft recursion

Abstract

The invention relates to a synchronous phasor calculation method based on DFT recursion of FPGA hardware. An FPGA is configured through a central processing unit (CPU) and controls an analog-digital (AD) converter to complete a sampling process under the 1 pulse per second signal (1PPS) synchronization, and the cycle DFT calculation and the recursion DFT calculation are utilized for eliminating accumulated errors of the recursion DFT calculation; and a complex phasor compensation algorithm is completed by the CPU. The FPGA and the CPU are matched to complete an acquisition calculation compensation process of synchronous phasors, and both the high-speed parallel computing capability of the FPGA and the flexible floating-point operation function of the CPU are used. The recursion DFP operation which is long in consumed time is completed by the FPGA, and the CPU loads are small, so that the communication response instantaneity of the CPU is guaranteed, and further, the communication reliability of a power management unit (PMU) is improved.

Description

technical field [0001] The invention discloses a synchrophasor calculation method based on FPGA hardware DFT recursion, belonging to the technical field of power system automatic measurement. Background technique [0002] With the continuous development of my country's power grid construction, the grid structure is becoming more and more perfect and more complex. There is an urgent need for new technical means to strengthen the dynamic security monitoring capabilities of the power grid and improve the security and stability of the power grid. The traditional SCADA system collects steady-state data refreshed at the second level, and the fault recorder provides fast transient waveform data within a period of time before and after the fault. There is no way to provide dynamic phasor data collected synchronously across the entire network. The synchronized phasor measurement unit (PMU) uses the satellite synchronous clock system to provide uniform sampling pulse and standard time...

AI Technical Summary

Problems solved by technology

Such traditional processing methods often lead to high CPU load, and the synchrophasor data packets sent to the master station may not be sent evenly, which is not conducive to the data processing of the master station

At the same time, the traditional DFT recursive operation has the problem of error accumulation, especially in the case of floating point operation, it is easy to cause the error of the calculation result to become larger

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