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Semiconductor chip and manufacturing method thereof

A semiconductor and wafer technology, applied in the field of semiconductor wafers and their preparation, can solve the problems of affecting the shape of a columnar semiconductor structure, affecting the withstand voltage characteristics and reliability of the wafer, etc., and achieve the effects of compact product structure, reduced production cost, and simple production process

Inactive Publication Date: 2013-04-03
朱江 +1
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The manufacturing process of semiconductor wafers with such a super-junction structure requires multiple anisotropic dry etching processes to control the distribution of columnar P-type semiconductors and N-type semiconductor regions, which easily affects the shape of the columnar semiconductor structure, thereby affecting the withstand voltage characteristics of the wafer. and reliability

Method used

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  • Semiconductor chip and manufacturing method thereof
  • Semiconductor chip and manufacturing method thereof
  • Semiconductor chip and manufacturing method thereof

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Embodiment

[0021] figure 1 It is a schematic cross-sectional view of a semiconductor wafer of the present invention, combined below figure 1 The semiconductor device of the present invention will be described in detail.

[0022] A semiconductor wafer with a super junction structure, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E20cm-3; a first semiconductor layer 2, which is located on the substrate layer 1, is N Conductive type semiconductor silicon material with a width of 4 μm, a thickness of 20 μm, and a doping concentration of phosphorus atoms of 1E16 cm-3; the second semiconductor layer 3, located on the sidewall of the first semiconductor layer 2 and the surface of the substrate layer 1, is of P conductivity type The semiconductor silicon material has a width of 2 μm and a thickness of 20 μm, and the doping concentration of boron atoms is 1E16 cm −3 ; the insulating layer 4 ...

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Abstract

The invention discloses a semiconductor chip with an ultra-junction structure, and a manufacturing method thereof. Manufacturing of an apparatus can be achieved by fewer secondary photoetching technologies and dry etching techniques. Even impurity concentration distribution in good columnar P-type semiconductor and N-type semiconductor areas and vertical direction can be achieved, and reverse voltage endurance of the chip and the reliability of the apparatus are improved.

Description

technical field [0001] The invention relates to a semiconductor wafer and a preparation method thereof, in particular to a semiconductor wafer capable of realizing high withstand voltage and low conduction resistance and a preparation method thereof. Background technique [0002] The semiconductor wafer structure capable of achieving high withstand voltage and low on-resistance is a structure in which columnar P-type semiconductors and N-type semiconductor regions are alternately arranged side by side, and the columnar P-type semiconductors and N-type semiconductors are perpendicular to the wafer surface. By setting the impurity concentration and width of the P-type semiconductor and the N-type semiconductor to desired values, a high breakdown voltage can be realized when a reverse voltage drop is applied. Such a structure is called a superjunction structure. [0003] Known super junction structure semiconductor wafer structure and manufacturing method are as follows: [0...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/02H01L21/20
Inventor 朱江盛况
Owner 朱江
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