Semiconductor chip and manufacturing method thereof

[0020] Example

[0021] figure 1 It is a schematic cross-sectional view of a semiconductor wafer of the present invention. figure 1 The semiconductor device of the present invention will be described in detail.

[0022] A semiconductor wafer with a super junction structure, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E20cm-3; a first semiconductor layer 2, which is located on the substrate layer 1, is N Conductive semiconductor silicon material with a width of 4μm and a thickness of 20μm. The doping concentration of phosphorus atoms is 1E16cm-3; the second semiconductor layer 3, located on the sidewall of the first semiconductor layer 2 and the surface of the substrate layer 1, is of P conductivity type The semiconductor silicon material has a width of 2 μm and a thickness of 20 μm, and the doping concentration of boron atoms is 1E16 cm-3; the insulating layer 4 is located in the groove of the second semiconductor layer 3 and is an oxide of semiconductor silicon material.

[0023] The manufacturing process includes the following steps:

[0024] In the first step, a phosphorus atom doped epitaxial layer is grown on the surface of the semiconductor silicon material substrate layer 1 with a phosphorus atom doping concentration of 1E20cm-3 to form a first semiconductor layer 2, such as figure 2 Shown

[0025] The second step is to perform high-temperature oxidation to form an oxide layer 5 on the surface of the epitaxial layer, and then remove part of the surface oxide layer 5 through a photolithography etching process, such as image 3 Shown

[0026] The third step is to form a plurality of trenches in the first semiconductor layer 2 through an anisotropic dry etching process, perform high-temperature oxidation again, and remove the surface oxide layer, such as Figure 4 Shown

[0027] In the fourth step, an epitaxial layer doped with boron atoms is grown to form a second semiconductor layer 3, such as Figure 5 Shown

[0028] The fifth step is to deposit silicon dioxide to form an insulating layer 4, such as Image 6 Shown

[0029] In the sixth step, the surface is polished, and the depth of the polishing is to expose the first semiconductor layer 2 on the surface, such as figure 1 Shown.

[0030] As mentioned above, by adopting the structure and manufacturing method of the above embodiments, compared with the prior art, fewer photolithography processes and anisotropic dry etching processes can be used to achieve device manufacturing, and the production process is simpler. Product structure It is more compact, reduces the production cycle of the device, and reduces the production cost of the device.

[0031] In the semiconductor wafer with a super junction structure of the present invention, the columnar P-type semiconductor and N-type semiconductor regions are composed of epitaxial layers, and the impurity concentration of the columnar P-type semiconductor and N-type semiconductor region can be uniformly distributed in the vertical direction. The semiconductor and N-type semiconductor regions are formed by an anisotropic dry etching process. It is easier to control the columnar structure of the P-type semiconductor and the N-type semiconductor region in the process, and it is easy to form a structure that can be perpendicular to the semiconductor wafer at the junction surface of the PN junction. Therefore, it is possible to provide a super-junction semiconductor wafer with a uniform expansion of the depletion layer, which improves the reverse withstand voltage characteristics of the wafer and the reliability of the device.