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Formation method of trench gate

A technology of trench gate and polysilicon gate, which is applied in the direction of semiconductor devices, can solve the problems of silicon wafer deformation and process influence, and achieve the effects of reducing stress, improving product yield and eliminating influence

Active Publication Date: 2015-06-03
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In addition, after the trench is filled, the polysilicon will shrink after the subsequent heat treatment (generally the diffusion of ion implantation), which will cause the side wall of the trench to be pulled towards the inside of the trench. The deeper the trench, the wider the trench width. The greater the tensile force, it will cause the deformation of the silicon wafer, which may affect the subsequent process

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  • Formation method of trench gate
  • Formation method of trench gate
  • Formation method of trench gate

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Embodiment Construction

[0031] Such as figure 2 It is a flowchart of a method for forming a trench gate according to an embodiment of the present invention; Figure 3A to Figure 3H Shown is a schematic diagram of the structure of the device in each step of the method for forming the trench gate according to the embodiment of the present invention. The method for forming the trench gate in the embodiment of the present invention includes the following steps:

[0032] Step 1, such as Figure 3A As shown, a first dielectric layer 2 is formed on a semiconductor substrate 1; the first dielectric layer 2 is SiO 2 , SiN, SiON, Al 2 o 3 , TaN, Ta 2 o 5 , HfO 2 , La 2 o 3 , Nb 2 o 5 , ZrO 2 at least one of the In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.

[0033] Step two, such as Figure 3B As shown, a polysilicon layer 3 is formed on the first dielectric layer 2 .

[0034] Step three, such as Figure 3C As shown, a second dielectric laye...

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Abstract

The invention discloses a formation method of a trench gate. The method includes a step of forming a first dielectric layer on a semiconductor substrate, a step of forming a polycrystalline silicon layer, a step of forming a second dielectric layer, a step of forming a polysilicon gate on a trench gate region through lithography etching, a step of annealing of polycrystalline silicon, a step of depositing a third dielectric layer, a step of selectively etching the third dielectric layer, a step of selectively epitaxial growing, wherein a semiconductor epitaxial layer is formed on the semiconductor substrate outside the trench gate region and the trench gate is composed of a portion of the polysilicon gate, wherein the portion of the polysilicon gate is sunken in the semiconductor epitaxial layer, and a step of wiping off the second dielectric layer on the top of the polysilicon gate. The formation method of the trench gate has the advantages of being capable of removing cavities of the trench gate and reducing stress of the polycrystalline silicon of the trench gate.

Description

technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a method for forming a trench gate. Background technique [0002] In order to save costs and improve performance, the unit size of integrated circuits is gradually shrinking. The gate technology has developed from the original planar technology to the trench gate technology, and the size of the trench gate is getting smaller and smaller, resulting in the AR of the trench. (The aspect ratio) is getting bigger and bigger. When polysilicon is used to fill the trench, because the top of the trench grows faster and the bottom of the trench grows slower, it is easy to cause voids in the trench to remain, which affects the performance of the device; and When the polysilicon outside the trench is subsequently removed, it is easy to open the cavity inside the trench, causing problems in the subsequent process. Such as Figure 1A to Figure 1D Shown is...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
Inventor 刘继全
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP