Packaging substrate and its manufacturing process, semiconductor element packaging structure and manufacturing process

Abstract

The invention discloses a packaging substrate, a manufacturing process of the packaging substrate, a packaging structure and a manufacturing process of a semiconductor element. The package substrate includes a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad. The dielectric layer has an upper surface and a lower surface. The first conductive layer is embedded in the dielectric layer and exposes a first surface on the upper surface. The first surface is flush with the upper surface. The second conductive layer is embedded in the dielectric layer and contacts the first conductive layer, and exposes a second surface on the lower surface. The second surface is flush with the lower surface. The bonding pad is partially or completely buried in the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is simultaneously limited in the cavity by the sidewalls of the first conductive layer and the dielectric layer.

Description

technical field [0001] The invention relates to a packaging structure and a manufacturing process, and in particular to a packaging substrate, a manufacturing process of the packaging substrate, a packaging structure of a semiconductor element and a manufacturing process thereof. Background technique [0002] With the widespread application of electronic products in daily life, the demand for semiconductor components is increasing day by day. Due to the thinner design of semiconductor components, when the size of semiconductor components shrinks, the number of I / O pins does not decrease but increases, which reduces the line pitch and line width, and develops towards the design of fine pitch, such as 50μm pitch , even below 35μm pitch. [0003] However, during the process of flip-chip assembling the semiconductor device on the packaging substrate, a bridging short circuit occurs between two adjacent conductive bumps due to high temperature reflow of the solder. In addition,...

AI Technical Summary

Problems solved by technology

[0003] However, in the process of flip-chip assembling the semiconductor element on the packaging substrate, a bridging short circuit occurs between two adjacent conductive bumps due to high-temperature reflow of the solder.

In addition, the solder has no solder mask covering the circuit layer to restrict its flow, so that the solder is easy to spread outward along the circuit layer (overspreading) when the solder is reflowed at high temperature, resulting in the gap between the flip-chip semiconductor element and the package substrate. The height is reduced, and due to the height reduction, it is difficult to fill the primer layer between the semiconductor element and the packaging substrate, resulting in a decrease in the reliability of the package, etc.

Images